d003d479ff
Update code from upstream repository https://github.com/lowRISC/opentitan to revision da3ac7c4eb23a92194874ad2daf2e5f9e3330572 * [memutil] Allow use without scrambled memories (Philipp Wagner) * [prim_prince] Fix comment (Philipp Wagner) * [memutil] Fix width mismatch (Philipp Wagner) * [prim] Allow disabling SVAs ensuring REQ is held until ACK at run time (Pirmin Vogel) * [prim] Fix typo that caused fifo_async to get stuck (Timothy Chen) * [prim] Add a missing ROM_CFG_DEFAULT to prim_rom_pkg.sv (Rupert Swarbrick) * [dvsim] Do not assume the build failed if "ERROR" is printed (Philipp Wagner) * [prim_subreg_shadow] Invert meaning of SWACCESS in shadow/stage regs (Michael Schaffner) * [prim_arb_tree/rv_plic_target] Remove TODOs due to a Vivado tool bug (Michael Schaffner) * [primgen] Remove unused import (Philipp Wagner) * [primgen] Add shebang (Philipp Wagner) * [primgen] Make primgen "portable" again (Philipp Wagner) * [dv] Small optimization in memutil (Philipp Wagner) * [tools/ascent] updated ascent to use the --job-prefix option (Rasmus Madsen) * [otp_ctrl] Remove invalid command error (Michael Schaffner) * [tlul] Add some missing dependencies (Michael Schaffner) * [otbn/otp_ctrl] Replicate dmem scrambling keystream (Michael Schaffner) * [adc_ctrl] Various preparation steps for d2 (Timothy Chen) * [tools/dvsim] Fix some VCS flags (Guillermo Maturana) * Revert "[prim] Do remove prim_esc.core from the dependencies" (Rupert Swarbrick) * [prim] Remove dependency of prim:esc on a hardware block (Rupert Swarbrick) * [lint] prim_ram_1p_scr verilator lint fixes (Greg Chadwick) * [dv] Add scrambled_ecc32_mem_area for memutils (Greg Chadwick) * [dv] Add C++ memory scrambling model (Greg Chadwick) * [tools/dsim] Fix non-LRM compliant code (Guillermo Maturana) * [prim] Do remove prim_esc.core from the dependencies (Michael Schaffner) * [dv/dv_utils] Improvement on `max` function (Cindy Chen) * [alert_handler] Implement reverse ping feature (Michael Schaffner) * [prim_esc] Split the prims into their own core file (Michael Schaffner) * [dvsim] Fix GUI mode and launcher creation fixes (Srikrishna Iyer) * [dv/common] Stress_all_with_rand_reset apply reset concurrently (Cindy Chen) * [dv/all] update scoreboard `csr_addrs` accesses (Udi Jonnalagadda) * [dv/csr_utils] update unmapped_addr calculation (Udi Jonnalagadda) * [dv] Update intg alert names (Weicai Yang) * [dv, flash_ctrl] Fix the intr test (Srikrishna Iyer) * [prim_fifo_async] Fix a width calculation issue in case of Depth = 1 (Michael Schaffner) * [dv] Update VCS opt for uvm_hdl_* (Weicai Yang) * [dv, util] Make poll_for_stop() opt-in (Srikrishna Iyer) * [dvsim] Separate publish report option [PART1] (Cindy Chen) * [dv/kmac/sram] reduce iterations of smoke test (Udi Jonnalagadda) * [dv/stress_all_with_reset] Revert back IPs that uses apply_reset (Cindy Chen) * [dv/edn_reset] Fix apply_reset to concurrently deassert resets (Cindy Chen) * [dv] Update VCS cov merge opts (Srikrishna Iyer) * [dv] Add TL integrity error test for CSR (Weicai Yang) * [dv, chip] Remove USB clk driver (Srikrishna Iyer) * [script/dvsim] Update output folder (Cindy Chen) * [dv/edn_reset] Update IPs that overrides apply_reset task (Cindy Chen) * [dv/edn_reset] Fix stress_all_with_rand_reset error (Cindy Chen) * [dv/dv_base_scoreboard] remove duplicated code (Cindy Chen) * [otbn,dv] Teach otbn_memutil to track expected end address (Rupert Swarbrick) * [dv, dv_utils_pkg] Fix common int typedefs (Srikrishna Iyer) * [prim_lfsr] Fix spyglass lint warnings (Michael Schaffner) * [prim_clock_gating] Target 7series Xilinx devices (Philipp Wagner) * [dv/edn_rst] Add coverage to collect edn reset and dut reset (Cindy Chen) * [otp_ctrl/lc_ctrl] Add LC TAP register to control OTP test mechanisms (Michael Schaffner) * [prim_alert*/prim_esc*] Rework placement of size_only bufs/flops (Michael Schaffner) * [dv] fix a typo in tl_device_access_types_testplan (Weicai Yang) * [prim_otp] Rework generic model to match new error behavior (Michael Schaffner) * [dv/tlul_common_test] Add a testplan for TLUL integrity check (Cindy Chen) * [dvsim] Allow recursive testplan import (Srikrishna Iyer) * [primgen] Use verible-verilog-syntax for parsing (Mariusz Glebocki) * [prim] Break always_comb block to avoid apparent loop (Rupert Swarbrick) * [dvsim] Fix testplan bugs (Srikrishna Iyer) * [fpv] update secded_gen (Cindy Chen) * [dv/template] small fixes on index.md format (Cindy Chen) * [prim_otp] Add a waiver for power signal unused in generic prim (Michael Schaffner) * [simutil_verilator] Improve timeout handling (Rupert Swarbrick) * [testplans] Rename entries with testpoints (Srikrishna Iyer) * [dvsim/testplan] Fix the rendered testplan (Srikrishna Iyer) * [dv/cov] exclude prim_lfsr and prim_prince (Udi Jonnalagadda) Signed-off-by: Philipp Wagner <phw@lowrisc.org> |
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| .github/ISSUE_TEMPLATE | ||
| ci | ||
| doc | ||
| dv | ||
| examples | ||
| formal | ||
| lint | ||
| rtl | ||
| shared | ||
| syn | ||
| util | ||
| vendor | ||
| .clang-format | ||
| .gitignore | ||
| .svlint.toml | ||
| azure-pipelines.yml | ||
| check_tool_requirements.core | ||
| CONTRIBUTING.md | ||
| CREDITS.md | ||
| ibex_configs.yaml | ||
| ibex_core.core | ||
| ibex_icache.core | ||
| ibex_multdiv.core | ||
| ibex_pkg.core | ||
| ibex_top.core | ||
| ibex_top_tracing.core | ||
| ibex_tracer.core | ||
| LICENSE | ||
| Makefile | ||
| python-requirements.txt | ||
| README.md | ||
| src_files.yml | ||
| tool_requirements.py | ||
Ibex RISC-V Core
Ibex is a production-quality open source 32-bit RISC-V CPU core written in SystemVerilog. The CPU core is heavily parametrizable and well suited for embedded control applications. Ibex is being extensively verified and has seen multiple tape-outs. Ibex supports the Integer (I) or Embedded (E), Integer Multiplication and Division (M), Compressed (C), and B (Bit Manipulation) extensions.
The block diagram below shows the small parametrization with a 2-stage pipeline.
Ibex was initially developed as part of the PULP platform under the name "Zero-riscy", and has been contributed to lowRISC who maintains it and develops it further. It is under active development.
Configuration
Ibex offers several configuration parameters to meet the needs of various application scenarios. The options include different choices for the architecture of the multiplier unit, as well as a range of performance and security features. The table below indicates performance, area and verification status for a few selected configurations. These are configurations on which lowRISC is focusing for performance evaluation and design verification (see supported configs).
| Config | "micro" | "small" | "maxperf" | "maxperf-pmp-bmfull" |
|---|---|---|---|---|
| Features | RV32EC | RV32IMC, 3 cycle mult | RV32IMC, 1 cycle mult, Branch target ALU, Writeback stage | RV32IMCB, 1 cycle mult, Branch target ALU, Writeback stage, 16 PMP regions |
| Performance (CoreMark/MHz) | 0.904 | 2.47 | 3.13 | 3.05 |
| Area - Yosys (kGE) | 17.44 | 26.06 | 35.64 | 58.74 |
| Area - Commercial (estimated kGE) | ~16 | ~24 | ~33 | ~54 |
| Verification status | Red | Green | Amber | Amber |
Notes:
- Performance numbers are based on CoreMark running on the Ibex Simple System platform.
Note that different ISAs (use of B and C extensions) give the best results for different configurations.
See the Benchmarks README for more information.
The "maxperf-pmp-bmfull" configuration sets a
SpecBranchparameter inibex_core.sv; this helps timing but has a small negative performance impact. - Yosys synthesis area numbers are based on the Ibex basic synthesis flow using the latch-based register file.
- Commercial synthesis area numbers are a rough estimate of what might be achievable with a commercial synthesis flow and technology library.
- For comparison, the original "Zero-riscy" core yields an area of 23.14kGE using our Yosys synthesis flow.
- Verification status is a rough guide to the overall maturity of a particular configuration. Green indicates that verification is close to complete. Amber indicates that some verification has been performed, but the configuration is still experimental. Red indicates a configuration with minimal/no verification. Users must make their own assessment of verification readiness for any tapeout.
- v0.92 of the RISC-V Bit Manipulation Extension is supported. This is not ratified and there may be changes for the v1.0 ratified version. See Standards Compliance in the Ibex documentation for more information.
Documentation
The Ibex user manual can be
read online at ReadTheDocs. It is also contained in
the doc folder of this repository.
Contributing
We highly appreciate community contributions. To ease our work of reviewing your contributions, please:
- Create your own branch to commit your changes and then open a Pull Request.
- Split large contributions into smaller commits addressing individual changes or bug fixes. Do not mix unrelated changes into the same commit!
- Write meaningful commit messages. For more information, please check out the contribution guide.
- If asked to modify your changes, do fixup your commits and rebase your branch to maintain a clean history.
When contributing SystemVerilog source code, please try to be consistent and adhere to our Verilog coding style guide.
When contributing C or C++ source code, please try to adhere to the OpenTitan C++ coding style
guide.
All C and C++ code should be formatted with clang-format before committing.
Either run clang-format -i filename.cc or git clang-format on added files.
To get started, please check out the "Good First Issue" list.
Issues and Troubleshooting
If you find any problems or issues with Ibex or the documentation, please check out the issue tracker and create a new issue if your problem is not yet tracked.
Questions?
Do not hesitate to contact us, e.g., on our public Ibex channel on Zulip!
License
Unless otherwise noted, everything in this repository is covered by the Apache License, Version 2.0 (see LICENSE for full text).
Credits
Many people have contributed to Ibex through the years. Please have a look at the credits file and the commit history for more information.