Tom Roberts d5ee96fff6 [rtl] Add dummy instruction insertion ... - Adds a new module in the IF stage to inject dummy instructions into the pipeline - Control / frequency of insertion is governed by configuration CSRs - Extra CSR added to allow reseed of the internal LFSR useed for randomizing insertion - Extra logic added to the register file to make dummy instruction writebacks look like real intructions (via the zero register) Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>		2020-05-21 13:58:01 +01:00
..
fpga/xilinx	Use shared code for Arty A7-100T example	2019-11-14 13:20:19 +01:00
sim	Make exiting from simple_system tests work with Spike	2020-03-02 15:45:47 +00:00
bus.sv	[dv] Fix Xcelium compilation	2020-04-25 17:59:32 +01:00
prim_assert.sv	[rtl] Modify ASSERT_KNOWN uses to work with xprop	2020-04-07 09:08:26 +01:00
prim_clock_gating.sv	[dv] Remove clock gating primitive in dv/uvm/tb	2019-11-16 00:25:32 +01:00
prim_generic_ram_1p.sv	[memutils] Add support for > 32b memories	2020-04-20 16:04:43 +01:00
prim_lfsr.sv	[rtl] Add dummy instruction insertion	2020-05-21 13:58:01 +01:00
prim_secded_28_22_dec.sv	[rtl] Add Icache ECC	2020-03-18 11:28:06 +00:00
prim_secded_28_22_enc.sv	[rtl] Add Icache ECC	2020-03-18 11:28:06 +00:00
prim_secded_72_64_dec.sv	[rtl] Add Icache ECC	2020-03-18 11:28:06 +00:00
prim_secded_72_64_enc.sv	[rtl] Add Icache ECC	2020-03-18 11:28:06 +00:00
ram_1p.sv	[dv] Fix Xcelium compilation	2020-04-25 17:59:32 +01:00
ram_2p.sv	[dv] Fix Xcelium compilation	2020-04-25 17:59:32 +01:00
timer.sv	Fix typo in signal declaration in timer.sv	2020-03-02 12:42:17 +00:00