e9a866ef55
Update code from upstream repository https://github.com/lowRISC/opentitan to revision affb06d8de0973bfdc271a6aa4b5ed7dc0b575bb * [dv] Add `wait_clks_or_rst` to `clk_rst_if` (Andreas Kurth) * [dv/cdc] Use cycle based CDC instrumentation (Guillermo Maturana) * [dv/prim_edn_req] Check data valid (Cindy Chen) * [rtl, chip dv] Coverage exclusions for pinmux / padring (Srikrishna Iyer) * [dv] Enhance probe function macro (Srikrishna Iyer) * [dv] enable loading `opentitan_flash_binary` images in DV (Timothy Trippel) * [prim_diff_decode] Update SVAs to make them compatible with sim CDC (Michael Schaffner) * [prim-lfsr] Fix DefaultSeedLocal compile scope (Srikrishna Iyer) * [dv] Update dv_base_reg_field to handle status interrupts (Weicai Yang) * [dvsim] fix bindgen error in nightlies (Timothy Trippel) * feat(prim): Add Status Interrupt type to `prim_intr_hw` (Eli Kim) * [dv/shadow_reg] Add coverplan for shadow reg (Cindy Chen) * [dv/shadow_reg] Add shadow reg fcov (Cindy Chen) * [dv/chip] Skip creating dv_base_reg coverage (Cindy Chen) * [chip, dv] Remove a testpoint - tl_intg_err (Weicai Yang) * [dv/top] Add option to automatically set rom_exec_en (Timothy Chen) * [dv] Use positive check in DV_CHECK* macros (Srikrishna Iyer) * [top/dv] Add plusargs to clear secret partitions (Michael Schaffner) * [dv/prim] Disable coverage for unused logic (Guillermo Maturana) * [dv] Add a global end-of-test signaling for RTL (Srikrishna Iyer) * [dv] Properly remove coverage on CDC rand delay module (Srikrishna Iyer) * [prim_sync_reqack] Disable reset checks by default, enable inside OTBN (Pirmin Vogel) * [prim_sync_reqack] Modify/extend SVAs with respect to reset (Pirmin Vogel) * [dv/clkmgr] Add exclusions and coverage pragmas (Guillermo Maturana) * [prim] Simplify defensive coding (Timothy Chen) * [prim_mubi] Fix sampling issue in MUBI sync assertions (Michael Schaffner) * [rtl/prim] Fix some prim_esc_receiver SVAs (Guillermo Maturana) * refactor(prim): rst_sync to have scanchain (Eli Kim) * [unr] Use elite license (Cindy Chen) * feat(prim): prim_rst_sync (Eli Kim) * refactor(dvsim): Remove `verdi` checker (Eli Kim) * [mubi/lc] Relax transient SVA checks (Michael Schaffner) * [fpv] fix random seed syntax error (Cindy) * [doc] Fix typos in //hw/lint and //hw/top_earlgrey (Dan McArdle) * [doc] Fix typos in //hw/ip (Dan McArdle) * [doc] Fix trailing whitespace before editing Markdown (Dan McArdle) * [dv/shadow_reg] Update comment (Cindy Chen) * [dv] Add macro `DV_CHECK_Q_EQ` (Weicai Yang) * [fpv/pwrmgr] Add assertions to check escalation (Cindy Chen) * [dv] Fix clk_rst_if limitation (Srikrishna Iyer) * [dv, pins_if] Add disconnect() method (Srikrishna Iyer) * SunGrid launcher support (Sharon Topaz) * [chip dv] Fix errors due to use of invalid HIER macros (Srikrishna Iyer) * [dv, clk_rst_if] Expand instance name in context (Srikrishna Iyer) * [dv] pins_if improvement (Srikrishna Iyer) * [CDC/PRIM] Updated prim_fifo_sync and prim_fifo_async to avoid CDC in rdata (Joshua Park) * Fix various typos in Markdown files (Dan McArdle) * [dvsim] Promote xcelium warning ENUMERR to an error (Michael Schaffner) * [dvsim] Install a SIGTERM handler (Srikrishna Iyer) * [flash_ctrl,dv] Enable random device param for all tests (Jaedon Kim) * [prim] Patch up design to help with coverage (Timothy Chen) * [flash_ctrl] Use comportable channels for alerts emanating from prim_flash (Michael Schaffner) * [doc, prim] doc update for new prim library (Joshua Park) * [otp_ctrl] Use comportable channels for alerts emanating from prim_otp (Michael Schaffner) * [dv] Replace wait_timeout with DV_WAIT_TIMEOUT (Weicai Yang) * [prim_lfsr] Initial block label (Srikrishna Iyer) * [dv/top] Regression triage (Timothy Chen) * [prim_lfsr] Enable randomization of initial seed (Srikrishna Iyer) * [dv] Fix timeout log (Weicai Yang) Signed-off-by: Andreas Kurth <adk@lowrisc.org> |
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| ci | ||
| doc | ||
| dv | ||
| examples | ||
| formal | ||
| lint | ||
| rtl | ||
| shared | ||
| syn | ||
| util | ||
| vendor | ||
| .clang-format | ||
| .gitignore | ||
| .svlint.toml | ||
| __init__.py | ||
| azure-pipelines.yml | ||
| check_tool_requirements.core | ||
| CONTRIBUTING.md | ||
| CREDITS.md | ||
| ibex_configs.yaml | ||
| ibex_core.core | ||
| ibex_icache.core | ||
| ibex_multdiv.core | ||
| ibex_pkg.core | ||
| ibex_top.core | ||
| ibex_top_tracing.core | ||
| ibex_tracer.core | ||
| LICENSE | ||
| Makefile | ||
| python-requirements.txt | ||
| README.md | ||
| src_files.yml | ||
| tool_requirements.py | ||
Ibex RISC-V Core
Ibex is a production-quality open source 32-bit RISC-V CPU core written in SystemVerilog. The CPU core is heavily parametrizable and well suited for embedded control applications. Ibex is being extensively verified and has seen multiple tape-outs. Ibex supports the Integer (I) or Embedded (E), Integer Multiplication and Division (M), Compressed (C), and B (Bit Manipulation) extensions.
The block diagram below shows the small parametrization with a 2-stage pipeline.
Ibex was initially developed as part of the PULP platform under the name "Zero-riscy", and has been contributed to lowRISC who maintains it and develops it further. It is under active development.
Configuration
Ibex offers several configuration parameters to meet the needs of various application scenarios. The options include different choices for the architecture of the multiplier unit, as well as a range of performance and security features. The table below indicates performance, area and verification status for a few selected configurations. These are configurations on which lowRISC is focusing for performance evaluation and design verification (see supported configs).
| Config | "micro" | "small" | "maxperf" | "maxperf-pmp-bmfull" |
|---|---|---|---|---|
| Features | RV32EC | RV32IMC, 3 cycle mult | RV32IMC, 1 cycle mult, Branch target ALU, Writeback stage | RV32IMCB, 1 cycle mult, Branch target ALU, Writeback stage, 16 PMP regions |
| Performance (CoreMark/MHz) | 0.904 | 2.47 | 3.13 | 3.13 |
| Area - Yosys (kGE) | 16.85 | 26.60 | 32.48 | 66.02 |
| Area - Commercial (estimated kGE) | ~15 | ~24 | ~30 | ~61 |
| Verification status | Red | Green | Amber | Amber |
Notes:
- Performance numbers are based on CoreMark running on the Ibex Simple System platform. Note that different ISAs (use of B and C extensions) give the best results for different configurations. See the Benchmarks README for more information.
- Yosys synthesis area numbers are based on the Ibex basic synthesis flow using the latch-based register file.
- Commercial synthesis area numbers are a rough estimate of what might be achievable with a commercial synthesis flow and technology library.
- For comparison, the original "Zero-riscy" core yields an area of 23.14kGE using our Yosys synthesis flow.
- Verification status is a rough guide to the overall maturity of a particular configuration. Green indicates that verification is close to complete. Amber indicates that some verification has been performed, but the configuration is still experimental. Red indicates a configuration with minimal/no verification. Users must make their own assessment of verification readiness for any tapeout.
- v.1.0.0 of the RISC-V Bit-Manipulation Extension is supported as well as the remaining sub-extensions of draft v.0.93 of the bitmanip spec. The latter are not ratified and there may be changes before ratification. See Standards Compliance in the Ibex documentation for more information.
Documentation
The Ibex user manual can be
read online at ReadTheDocs. It is also contained in
the doc folder of this repository.
Examples
The Ibex repository includes Simple System. This is an intentionally simple integration of Ibex with a basic system that targets simulation. It is intended to provide an easy way to get bare metal binaries running on Ibex in simulation.
A more complete example can be found in the Ibex Super System repository. In particular it includes a integration of the PULP RISC-V debug module. It targets the Arty A7 FPGA board from Digilent and supports debugging via OpenOCD and GDB over USB (no external JTAG probe required). The Ibex Super System is written by lowRISC but is not an official part of Ibex, nor officially supported by lowRISC.
Contributing
We highly appreciate community contributions. To ease our work of reviewing your contributions, please:
- Create your own branch to commit your changes and then open a Pull Request.
- Split large contributions into smaller commits addressing individual changes or bug fixes. Do not mix unrelated changes into the same commit!
- Write meaningful commit messages. For more information, please check out the contribution guide.
- If asked to modify your changes, do fixup your commits and rebase your branch to maintain a clean history.
When contributing SystemVerilog source code, please try to be consistent and adhere to our Verilog coding style guide.
When contributing C or C++ source code, please try to adhere to the OpenTitan C++ coding style
guide.
All C and C++ code should be formatted with clang-format before committing.
Either run clang-format -i filename.cc or git clang-format on added files.
To get started, please check out the "Good First Issue" list.
Issues and Troubleshooting
If you find any problems or issues with Ibex or the documentation, please check out the issue tracker and create a new issue if your problem is not yet tracked.
Questions?
Do not hesitate to contact us, e.g., on our public Ibex channel on Zulip!
License
Unless otherwise noted, everything in this repository is covered by the Apache License, Version 2.0 (see LICENSE for full text).
Credits
Many people have contributed to Ibex through the years. Please have a look at the credits file and the commit history for more information.