Tom Roberts ef17d4fcc2 [rtl] Add Icache ECC ... - Add modules for ecc generation and checking - Add supporting logic to icache module Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>		2020-03-18 11:28:06 +00:00
..
fpga/xilinx	Use shared code for Arty A7-100T example	2019-11-14 13:20:19 +01:00
sim	Make exiting from simple_system tests work with Spike	2020-03-02 15:45:47 +00:00
bus.sv	[examples] Add Dual-Port Memory to Simple System	2020-01-29 16:50:52 +01:00
prim_assert.sv	Remove property from assert message	2020-03-13 10:47:40 +00:00
prim_clock_gating.sv	[dv] Remove clock gating primitive in dv/uvm/tb	2019-11-16 00:25:32 +01:00
prim_generic_ram_1p.sv	[rtl] Icache RAM primitive changes	2020-03-18 11:28:06 +00:00
prim_secded_28_22_dec.sv	[rtl] Add Icache ECC	2020-03-18 11:28:06 +00:00
prim_secded_28_22_enc.sv	[rtl] Add Icache ECC	2020-03-18 11:28:06 +00:00
prim_secded_72_64_dec.sv	[rtl] Add Icache ECC	2020-03-18 11:28:06 +00:00
prim_secded_72_64_enc.sv	[rtl] Add Icache ECC	2020-03-18 11:28:06 +00:00
ram_1p.sv	Reverse return code of simutil_verilator_set_mem()	2019-11-28 18:45:11 +00:00
ram_2p.sv	[examples] Add Dual-Port Memory to Simple System	2020-01-29 16:50:52 +01:00
timer.sv	Fix typo in signal declaration in timer.sv	2020-03-02 12:42:17 +00:00