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Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
| include | ||
| tb/serDiv | ||
| .gitignore | ||
| alu.sv | ||
| compressed_decoder.sv | ||
| controller.sv | ||
| cs_registers.sv | ||
| debug_unit.sv | ||
| decoder.sv | ||
| ex_stage.sv | ||
| exc_controller.sv | ||
| id_stage.sv | ||
| if_stage.sv | ||
| LICENSE | ||
| load_store_unit.sv | ||
| prefetch_buffer.sv | ||
| prefetch_L0_buffer.sv | ||
| README.md | ||
| register_file.sv | ||
| register_file_ff.sv | ||
| riscv_simchecker.sv | ||
| riscv_tracer.sv | ||
| src_files.yml | ||
| zeroriscy_core.sv | ||
| zeroriscy_tracer.sv | ||
zero-riscy: RISC-V Core
zero-riscy is a small 3-stage RISC-V core derivated by littleRISCV.
zero-riscy fully implements the RV32IC instruction set and it is meant for control code.