Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

cpucorehardwarerisc-vrv32

Sven Stucki ff712bf367 Improved instruction tracer, added custom instruction for core id		2015-04-20 11:21:02 +02:00
include	Improved instruction tracer, added custom instruction for core id	2015-04-20 11:21:02 +02:00
alu.sv	Fixed Jumps and Branches (jump target now calculated in ID, up for debate) and some general code cleanups	2015-04-15 18:27:51 +02:00
controller.sv	Improved instruction tracer, added custom instruction for core id	2015-04-20 11:21:02 +02:00
debug_unit.sv	Initial RiscV core commit; still in an early stage, but ALU instructions work	2015-04-01 11:11:07 +02:00
ex_stage.sv	Reimplemented jumps/branches in a more intelligent way; prevent forwarding of x0	2015-04-19 02:34:43 +02:00
id_stage.sv	Reimplemented jumps/branches in a more intelligent way; prevent forwarding of x0	2015-04-19 02:34:43 +02:00
if_stage.sv	Reimplemented jumps/branches in a more intelligent way; prevent forwarding of x0	2015-04-19 02:34:43 +02:00
instr_core_interface.sv	Fixed space/tab mixture and indentation in instr_core_interface	2015-04-16 15:21:03 +02:00
load_store_unit.sv	Initial RiscV core commit; still in an early stage, but ALU instructions work	2015-04-01 11:11:07 +02:00
mult.sv	Initial RiscV core commit; still in an early stage, but ALU instructions work	2015-04-01 11:11:07 +02:00
register_file.sv	Initial RiscV core commit; still in an early stage, but ALU instructions work	2015-04-01 11:11:07 +02:00
riscv_core.sv	Improved instruction tracer, added custom instruction for core id	2015-04-20 11:21:02 +02:00
wb_stage.sv	Initial RiscV core commit; still in an early stage, but ALU instructions work	2015-04-01 11:11:07 +02:00