[docs/ug] added Xilinx IP block designer

docs/userguide/content.adoc

@@ -793,11 +793,25 @@ any user interaction.
 :sectnums:
 == Packaging the Processor as IP block for Xilinx Vivado Block Designer
 
-.WORK IN PROGRESS
-[WARNING]
-This Section Is Under Construction! +
- +
-FIXME!
+[start=1]
+. Import all the core files from `rtl/core` and assign them to a _new_ design library `neorv32`.
+. Instantiate the `rtl/wrappers/neorv32_top_axi4lite.vhd` module.
+. Then either directly use that module in a new block-design ("Create Block Design", right-click -> "Add Module",
+thats easier for a first try) or package it ("Tools", "Create and Package new IP") for the use in other projects.
+. Connect your AXI-peripheral directly to the core's AXI4-Interface if you only have one, or to an AXI-Interconnect
+(from the IP-catalog) if you have multiple peripherals.
+. Connect ALL the `ACLK` and `ARESETN` pins of all peripherals and interconnects to the processor's clock and reset
+signals to have a _unified_ clock and reset domain (easier for a first setup).
+. Open the "Address Editor" tab and let Vivado assign the base-addresses for the AXI-peripherals (you can modify them
+according to your needs).
+. For all FPGA-external signals (like UART signals) make all the connections you need "external"
+(right-click on the signal/pin -> "Make External").
+. Save everything, let VIVADO create a HDL-Wrapper for the block-design and choose this as your _Top Level Design_.
+. Define your constraints and generate your bitstream.
+
+[NOTE]
+Guide provided by GitHub user https://github.com/AWenzel83[`AWenzel83`] from
+https://github.com/stnolting/neorv32/discussions/52#discussioncomment-819013