[rte] print ISA ext. in alphabetical order

This commit is contained in:
stnolting 2024-02-04 10:43:45 +01:00
parent 89d9f1b640
commit 0266a3783b

View file

@ -555,6 +555,10 @@ void neorv32_rte_print_hw_config(void) {
// CPU sub-extensions
tmp = neorv32_cpu_csr_read(CSR_MXISA);
if (tmp & (1<<CSR_MXISA_SDEXT)) { neorv32_uart0_printf("Sdext "); }
if (tmp & (1<<CSR_MXISA_SDTRIG)) { neorv32_uart0_printf("Sdtrig "); }
if (tmp & (1<<CSR_MXISA_SMCNTRPMF)) { neorv32_uart0_printf("Smcntrpmf "); }
if (tmp & (1<<CSR_MXISA_PMP)) { neorv32_uart0_printf("Smpmp "); }
if (tmp & (1<<CSR_MXISA_ZFINX)) { neorv32_uart0_printf("Zfinx "); }
if (tmp & (1<<CSR_MXISA_ZICNTR)) { neorv32_uart0_printf("Zicntr "); }
if (tmp & (1<<CSR_MXISA_ZICOND)) { neorv32_uart0_printf("Zicond "); }
@ -563,10 +567,6 @@ void neorv32_rte_print_hw_config(void) {
if (tmp & (1<<CSR_MXISA_ZIHPM)) { neorv32_uart0_printf("Zihpm "); }
if (tmp & (1<<CSR_MXISA_ZMMUL)) { neorv32_uart0_printf("Zmmul "); }
if (tmp & (1<<CSR_MXISA_ZXCFU)) { neorv32_uart0_printf("Zxcfu "); }
if (tmp & (1<<CSR_MXISA_SDEXT)) { neorv32_uart0_printf("Sdext "); }
if (tmp & (1<<CSR_MXISA_SDTRIG)) { neorv32_uart0_printf("Sdtrig "); }
if (tmp & (1<<CSR_MXISA_SMCNTRPMF)) { neorv32_uart0_printf("Smcntrpmf "); }
if (tmp & (1<<CSR_MXISA_PMP)) { neorv32_uart0_printf("Smpmp "); }
// CPU tuning options
neorv32_uart0_printf("\nTuning options: ");
if (tmp & (1<<CSR_MXISA_FASTMUL)) { neorv32_uart0_printf("fast_mul "); }