[docs] cleanups

docs/attrs.adoc

@@ -1,3 +1,5 @@
+:author: The NEORV32 Community and Stephan Nolting
+:email: stnolting@gmail.com
 :keywords: neorv32, risc-v, riscv, rv32, fpga, soft-core, vhdl, microcontroller, cpu, soc, processor, gcc, openocd, gdb, verilog, rtl, asip, asic, safety
 :description: A size-optimized, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
 :revnumber: v1.10.5

docs/figures/README.md

@@ -1,6 +1,7 @@
 ## :copyright: Image License and Copyright Notifications
 
-Figures are own work if not otherwise stated; see the [project's license](https://github.com/stnolting/neorv32/blob/main/LICENSE).
+Figures are own work if not otherwise stated; see the
+[project's license](https://github.com/stnolting/neorv32/blob/main/LICENSE).
 No copyright infringement intended.
 
 - `SPI_timing_diagram2.wikimedia.png`
@@ -11,10 +12,6 @@ No copyright infringement intended.
   - source: https://riscv.org/risc-v-logo/
   - license: https://riscv.org/about/risc-v-branding-guidelines/
 
-- `oshw_logo.png`
-  - source: https://www.oshwa.org/open-source-hardware-logo/
-  - license: Creative Commons Attribution-ShareAlike 4.0 International License
-
 - `neorv32_logo_smcard.jpg`
   - source: background image by https://pixabay.com
   - license: Pixabay license

docs/legal.adoc

@@ -11,7 +11,7 @@
 https://github.com/stnolting/neorv32 +
 Stephan Nolting, M.Sc. +
 🇪🇺 European Union +
-`stnolting[ät]gmail[d0t]com`
+stnolting@gmail.com
 ==========================