github-mirrors/neorv32
1
0
Fork 0
mirror of https://github.com/stnolting/neorv32.git synced 2025-04-24 06:07:52 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

[sim] enable Zbkc extension in testbenches

Browse source
This commit is contained in:
stnolting 2024-09-27 21:40:07 +02:00
parent d0ab6b163d
commit 0a18dc3c0b
2 changed files with 2 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

1
sim/neorv32_tb.vhd
View file

@ -207,6 +207,7 @@ begin
CPU_EXTENSION_RISCV_M => true, -- implement mul/div extension?
CPU_EXTENSION_RISCV_U => true, -- implement user mode extension?
CPU_EXTENSION_RISCV_Zbkb => true, -- implement bit-manipulation instructions for cryptography
CPU_EXTENSION_RISCV_Zbkc => true, -- implement carry-less multiplication instructions?
CPU_EXTENSION_RISCV_Zbkx => true, -- implement cryptography crossbar permutation extension?
CPU_EXTENSION_RISCV_Zfinx => true, -- implement 32-bit floating-point extension (using INT reg!)
CPU_EXTENSION_RISCV_Zicntr => true, -- implement base counters?

1
sim/simple/neorv32_tb.simple.vhd
View file

@ -179,6 +179,7 @@ begin
CPU_EXTENSION_RISCV_M => true, -- implement mul/div extension?
CPU_EXTENSION_RISCV_U => true, -- implement user mode extension?
CPU_EXTENSION_RISCV_Zbkb => true, -- implement bit-manipulation instructions for cryptography
CPU_EXTENSION_RISCV_Zbkc => true, -- implement carry-less multiplication instructions?
CPU_EXTENSION_RISCV_Zbkx => true, -- implement cryptography crossbar permutation extension?
CPU_EXTENSION_RISCV_Zfinx => true, -- implement 32-bit floating-point extension (using INT reg!)
CPU_EXTENSION_RISCV_Zicntr => true, -- implement base counters?