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[doc] updated online documentation
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@ -14,7 +14,7 @@ For the HDL sources the version number is globally defined by the `hw_version_c`
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| Date (*dd.mm.yyyy*) | Version | Comment |
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|:----------:|:-------:|:--------|
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| 23.10.2020 | 1.4.6.0 | Completely reworked external memory interface (WISHBONE), removed now-obsolete processor generic `MEM_EXT_REG_STAGES`; |
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| 23.10.2020 | 1.4.6.0 | Completely reworked external memory interface (WISHBONE), removed now-obsolete processor generic `MEM_EXT_REG_STAGES`; added processor wrapper with **AXI4-Lite master interface** |
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| 22.10.2020 | 1.4.5.11 | TWI: Added new control register flag to enable/disable SCL clock stretching by peripheral devices |
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| 22.10.2020 | 1.4.5.10 | Added `i_bus_priv_o` and `d_bus_priv_o` signals to CPU_top and `priv_o` to Processor_top to show privilege level of bus access (from `mstatus` MPP); :warning: Fixed bug in external memory interface [WISHBONE] (non-standard Wishbone components were able to corrupt processor-internal ACK/ERR signal logic) |
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| 20.10.2020 | 1.4.5.9 | :warning: Fixed bug in CPU "sleep" instruction (`WFI` - wait for interrupt) |
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43
README.md
43
README.md
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@ -4,9 +4,6 @@
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[](https://github.com/stnolting/neorv32/blob/master/LICENSE)
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[](https://github.com/stnolting/neorv32/releases)
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## Table of Content
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* [Overview](#Overview)
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* [Project Status](#Status)
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* [Features](#Features)
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@ -75,6 +72,7 @@ To see the changes between releases visit the project's [release page](https://g
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* Fully synchronous design, no latches, no gated clocks
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* Small hardware footprint and high operating frequency
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* Highly configurable CPU and processor setup
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* [AXI4-Lite connectivity](#AXI4-Connectivity) - compatible with Xilinx Vivado IP Packer
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* [FreeRTOS port](https://github.com/stnolting/neorv32/blob/master/sw/example/demo_freeRTOS) available
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@ -102,13 +100,13 @@ The processor passes the official `rv32i`, `rv32im`, `rv32imc`, `rv32Zicsr` and
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| [RISC-V compliance test](https://github.com/stnolting/neorv32_riscv_compliance) | [](https://travis-ci.com/stnolting/neorv32_riscv_compliance) | |
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### To-Do / Wish List
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### To-Do / Wish List / [Help Wanted](#Contribute)
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* Add a cache for the external memory interface
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* Use LaTeX for data sheet
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* Further size and performance optimization
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* Add AXI(-Lite) bridges
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* Synthesis results (+ wrappers?) for more platforms
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* Maybe port additional RTOSs (like [Zephyr](https://github.com/zephyrproject-rtos/zephyr) or [RIOT](https://www.riot-os.org))
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* Use LaTeX for data sheet
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* Implement further CPU extensions:
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* Atomic operations (`A`)
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* Bitmanipulation operations (`B`), when they are "official"
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@ -133,9 +131,10 @@ is highly customizable via the processor's top generics.
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* Optional machine system timer (**MTIME**), RISC-V-compliant
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* Optional universal asynchronous receiver and transmitter (**UART**) with simulation output option via text.io
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* Optional 8/16/24/32-bit serial peripheral interface controller (**SPI**) with 8 dedicated chip select lines
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* Optional two wire serial interface controller (**TWI**), compatible to the I²C standard
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* Optional two wire serial interface controller (**TWI**), with optional clock-stretching, compatible to the I²C standard
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* Optional general purpose parallel IO port (**GPIO**), 32xOut & 32xIn, with pin-change interrupt
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* Optional 32-bit external bus interface, Wishbone b4 compliant (**WISHBONE**), *standard* or *pipelined* handshake/transactions mode
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* Optional wrapper for **AXI4-Lite Master Interface** (see [`rtl/top_templates`](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates)), compatibility verified with Xilinx Vivado Block Desginer
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* Optional watchdog timer (**WDT**)
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* Optional PWM controller with 4 channels and 8-bit duty cycle resolution (**PWM**)
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* Optional GARO-based true random number generator (**TRNG**)
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@ -272,7 +271,7 @@ Results generated for hardware version `1.4.4.8`.
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| TWI | Two-wire interface | 74 | 44 | 0 | 0 |
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| UART | Universal asynchronous receiver/transmitter | 175 | 132 | 0 | 0 |
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| WDT | Watchdog timer | 58 | 45 | 0 | 0 |
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| WISHBONE | External memory interface (`MEM_EXT_REG_STAGES` = 2) | 106 | 104 | 0 | 0 |
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| WISHBONE | External memory interface | 106 | 104 | 0 | 0 |
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### NEORV32 Processor - Exemplary FPGA Setups
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@ -479,7 +478,6 @@ entity neorv32_top is
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MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes
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-- External memory interface --
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MEM_EXT_USE : boolean := false; -- implement external memory bus interface?
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MEM_EXT_REG_STAGES : natural := 2; -- number of interface register stages (0,1,2)
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-- Processor peripherals --
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IO_GPIO_USE : boolean := true; -- implement general purpose input/output port unit (GPIO)?
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IO_MTIME_USE : boolean := true; -- implement machine system timer (MTIME)?
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@ -535,6 +533,25 @@ end neorv32_top;
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```
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### AXI4 Connectivity
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Via the [`rtl/top_templates/neorv32_top_axi4lite.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates/neorv32_top_axi4lite.vhd)
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wrapper the NEORV32 provides an **AXI4-Lite** compatible master interface. This wrapper instantiates the default NEORV32 processor top entitiy
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and implements a bi-directional Wishbone to AXI4-Lite bridge.
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The AXI4-Lite interface has been tested using Xilinx Vivado 19.2 block designer:
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The processor was packed as custom IP using `neorv32_top_axi4lite.vhd` as top entity. The AXI interface is automatically detected by the packager.
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All remaining IO interfaces are available as custom signals. The configuration generics are available via the "customize IP" dialog.
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In the figure above the resulting IP block is named "neorv32_top_axi4lite_v1_0".
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The setup uses an AXI interconnect to attach two block RAMs to the processor. Since the processor in this example is configured *without* IMEM and DMEM,
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the attached block RAMs are used for storing instructions and data: the first RAM is used as instruction memory
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and is mapped to address `0x00000000 - 0x00003fff` (16kB), the second RAM is used as data memory and is mapped to address `0x80000000 - 0x80001fff` (8kB).
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## Getting Started
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@ -740,13 +757,11 @@ link in question.
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"Artix" and "Vivado" are trademarks of Xilinx Inc.
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"Cyclone", "Quartus Prime", "Quartus Prime Lite" and "Avalon Bus" are trademarks of Intel Corporation.
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"Cyclone", "Quartus Prime Lite" and "Avalon Bus" are trademarks of Intel Corporation.
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"Artix" and "Vivado" are trademarks of Xilinx, Inc.
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"iCE40", "UltraPlus" and "Radiant" are trademarks of Lattice Semiconductor Corporation.
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"iCE40", "UltraPlus" and "Lattice Radiant" are trademarks of Lattice Semiconductor Corporation.
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"AXI" and "AXI-Lite" are trademarks of Arm Holdings plc.
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"AXI", "AXI4" and "AXI4-Lite" are trademarks of Arm Holdings plc.
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