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[readme] add OCD authentication
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@ -198,6 +198,7 @@ data integrity (CRC8/16/32)
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* compatible to the "Minimal RISC-V Debug Specification Version 1.0"
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* compatible with **OpenOCD**, **GDB** and **Segger Embedded Studio**
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* RISC-V [trigger module](https://stnolting.github.io/neorv32/#_trigger_module) for hardware-assisted breakpoints
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* optional authentication module to implement custom security mechanisms
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## 3. FPGA Implementation Results
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