mirror of
https://github.com/stnolting/neorv32.git
synced 2025-04-23 21:57:33 -04:00
updated and optimized RTE - smaller, faster, better ;)
This commit is contained in:
stnolting
parent
8ade8ad170
commit
11f30c7885
4 changed files with 185 additions and 241 deletions
204
sw/common/crt0.S
204
sw/common/crt0.S
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@ -43,11 +43,11 @@
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// IO region
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.set IO_BEGIN, 0xFFFFFF80 // start of processor-internal IO region
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.equ IO_BEGIN, 0xFFFFFF80 // start of processor-internal IO region
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// SYSINFO
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.set SYSINFO_DSPACE_BASE, 0xFFFFFFF4
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.set SYSINFO_DSPACE_SIZE, 0xFFFFFFFC
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.equ SYSINFO_DSPACE_BASE, 0xFFFFFFF4
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.equ SYSINFO_DSPACE_SIZE, 0xFFFFFFFC
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_start:
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@ -58,9 +58,8 @@ _start:
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// Clear register file
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// *********************************************************
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__crt0_reg_file_clear:
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addi x0, x0, 0 // hardwired to zero
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//addi x0, x0, 0 // hardwired to zero
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addi x1, x0, 0
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__crt0_reg_file_init:
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addi x2, x1, 0
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addi x3, x2, 0
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addi x4, x3, 0
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@ -78,7 +77,7 @@ __crt0_reg_file_init:
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// the following registers do not exist in rv32e
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// "__RISCV_EMBEDDED_CPU__" is automatically defined by the makefiles when
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// compiling for a rv32e architecture
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// compiling for a rv32e* architecture
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#ifndef __RISCV_EMBEDDED_CPU__
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addi x16, x15, 0
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addi x17, x16, 0
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@ -100,7 +99,7 @@ __crt0_reg_file_init:
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// *********************************************************
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// TEST AREA / DANGER ZONE / IDEA-LAB
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// TEST AREA / DANGER ZONE
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// *********************************************************
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__crt0_tests:
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nop
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@ -128,22 +127,12 @@ __crt0_global_pointer_init:
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// *********************************************************
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// Init exception vector table (2x16 4-byte entries) with dummy handlers
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// Init trap handler base address
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// *********************************************************
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__crt0_neorv32_rte_init:
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la x11, __crt0_neorv32_rte
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__crt0_neorv32_trap_init:
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la x11, __crt0_dummy_trap_handler
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csrw mtvec, x11 // set address of first-level exception handler
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lw x11, SYSINFO_DSPACE_BASE(zero) // data memory space base address
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la x12, __crt0_neorv32_rte_dummy_hanlder
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li x13, 2*16 // number of entries (16xEXC, 16xIRQ)
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__crt0_neorv32_rte_init_loop:
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sw x12, 0(x11) // set dummy handler
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add x11, x11, 4
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add x13, x13, -1
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bne zero, x13, __crt0_neorv32_rte_init_loop
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// *********************************************************
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// Reset/deactivate IO/peripheral devices
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@ -216,167 +205,44 @@ __crt0_this_is_the_end_end:
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// *********************************************************
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// NEORV32 runtime environment: First-level exception/interrupt handler
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// dummy trap handler (for exceptions & IRQs)
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// tries to move on to next instruction
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// *********************************************************
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.align 4
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__crt0_neorv32_rte:
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.balign 4
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__crt0_dummy_trap_handler:
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// --------------------------------------------
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// full context save
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// --------------------------------------------
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#ifndef __RISCV_EMBEDDED_CPU__
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addi sp, sp, -120
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#else
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addi sp, sp, -56
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#endif
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addi sp, sp, -8
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sw x8, 0(sp)
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sw x9, 4(sp)
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sw ra,0(sp)
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sw gp,4(sp)
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sw tp,8(sp)
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sw t0,12(sp)
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sw t1,16(sp)
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sw t2,20(sp)
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sw s0,24(sp)
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sw s1,28(sp)
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sw a0,32(sp)
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sw a1,36(sp)
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sw a2,40(sp)
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sw a3,44(sp)
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sw a4,48(sp)
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sw a5,52(sp)
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#ifndef __RISCV_EMBEDDED_CPU__
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sw a6,56(sp)
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sw a7,60(sp)
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sw s2,64(sp)
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sw s3,68(sp)
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sw s4,72(sp)
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sw s5,76(sp)
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sw s6,80(sp)
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sw s7,84(sp)
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sw s8,88(sp)
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sw s9,92(sp)
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sw s10,96(sp)
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sw s11,100(sp)
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sw t3,104(sp)
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sw t4,108(sp)
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sw t5,112(sp)
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sw t6,116(sp)
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#endif
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csrr x8, mcause
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blt x8, zero, __crt0_dummy_trap_handler_irq // skip mepc modification if interrupt
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__crt0_dummy_trap_handler_compute_return:
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csrr x8, mepc
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// --------------------------------------------
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// get cause and prepare jump into vector table
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// --------------------------------------------
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csrr t0, mcause // get cause code
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// is compressed instruction?
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lh x9, 0(x8) // get compressed instruction or lower 16 bits of uncompressed instruction that caused exception
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andi x9, zero, 3 // mask: isolate lowest 2 opcode bits (= 11 for uncompressed instructions)
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andi t1, t0, 0x0f // isolate cause ID
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slli t1, t1, 2 // make address offset
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lw ra, SYSINFO_DSPACE_BASE(zero) // data memory space base address
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add t1, t1, ra // get vetor table entry address (EXC vectors)
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addi x8, x8, +2 // only this for compressed instructions
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csrw mepc, x8 // set return address when compressed instruction
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csrr ra, mepc // get return address
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blt t0, zero, __crt0_neorv32_rte_is_irq // branch if this is an INTERRUPT
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// --------------------------------------------
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// compute return address for EXCEPTIONS only
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// --------------------------------------------
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__crt0_neorv32_rte_is_exc:
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// check if faulting instruction is compressed and adjust return address
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lh t0, 0(ra) // get compressed instruction or lower 16 bits of uncompressed instruction that caused exception
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addi t2, zero, 3 // mask
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and t0, t0, t2 // isolate lowest 2 opcode bits (= 11 for uncompressed instructions)
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addi ra, ra, +2 // only this for compressed instructions
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bne t0, t2, __crt0_neorv32_rte_execute // jump if compressed instruction
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addi x8, zero, 3
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bne x8, x9, __crt0_dummy_trap_handler_irq // jump if compressed instruction
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addi ra, ra, +2 // add another 2 (making +4) for uncompressed instructions
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j __crt0_neorv32_rte_execute
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// is uncompressed instruction
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csrr x8, mepc
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addi x8, x8, +2 // add another 2 (making +4) for uncompressed instructions
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csrw mepc, x8
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__crt0_dummy_trap_handler_irq:
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// --------------------------------------------
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// vector table offset for INTERRUPTS only
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// --------------------------------------------
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__crt0_neorv32_rte_is_irq:
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addi t1, t1, 16*4
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lw x9, 0(sp)
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lw x8, 4(sp)
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addi sp, sp, +8
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// --------------------------------------------
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// call handler from vector table
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// --------------------------------------------
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__crt0_neorv32_rte_execute:
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lw t0, 0(t1) // get base address of second-level handler
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// push ra
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addi sp, sp, -4
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sw ra, 0(sp)
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jalr ra, t0 // call second-level handler
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// pop ra
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lw ra, 0(sp)
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addi sp, sp, +4
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csrw mepc, ra
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// --------------------------------------------
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// full context restore
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// --------------------------------------------
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lw ra,0(sp)
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lw gp,4(sp)
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lw tp,8(sp)
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lw t0,12(sp)
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lw t1,16(sp)
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lw t2,20(sp)
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lw s0,24(sp)
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lw s1,28(sp)
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lw a0,32(sp)
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lw a1,36(sp)
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lw a2,40(sp)
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lw a3,44(sp)
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lw a4,48(sp)
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lw a5,52(sp)
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#ifndef __RISCV_EMBEDDED_CPU__
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lw a6,56(sp)
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lw a7,60(sp)
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lw s2,64(sp)
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lw s3,68(sp)
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lw s4,72(sp)
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lw s5,76(sp)
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lw s6,80(sp)
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lw s7,84(sp)
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lw s8,88(sp)
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lw s9,92(sp)
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lw s10,96(sp)
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lw s11,100(sp)
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lw t3,104(sp)
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lw t4,108(sp)
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lw t5,112(sp)
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lw t6,116(sp)
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#endif
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#ifndef __RISCV_EMBEDDED_CPU__
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addi sp, sp, +120
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#else
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addi sp, sp, +56
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#endif
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// --------------------------------------------
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// this is the ONLY place where MRET should be used!
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// --------------------------------------------
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mret
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// *********************************************************
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// Dummy exception handler: just move on to next instruction
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// *********************************************************
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__crt0_neorv32_rte_dummy_hanlder:
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ret
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.cfi_endproc
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.end
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@ -53,9 +53,8 @@ SEARCH_DIR("=/opt/riscv/riscv64-unknown-linux-gnu/lib"); SEARCH_DIR("=/usr/local
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/* ************************************************* */
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MEMORY
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{
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rom (rx) : ORIGIN = 0x00000000, LENGTH = 16*1024
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ram (rwx) : ORIGIN = 0x80000000 + 2*16*4, LENGTH = 8*1024
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/* DO NOT REMOVE THE " + 2*16*4"!! */
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rom (rx) : ORIGIN = 0x00000000, LENGTH = 16*1024
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ram (rwx) : ORIGIN = 0x80000000, LENGTH = 8*1024
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}
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/* ************************************************* */
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@ -42,10 +42,32 @@
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#ifndef neorv32_rte_h
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#define neorv32_rte_h
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/**********************************************************************//**
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* RTE trap IDs.
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**************************************************************************/
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enum NEORV32_RTE_TRAP_enum {
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RTE_TRAP_I_MISALIGNED = 0, /**< Instruction address misaligned */
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RTE_TRAP_I_ACCESS = 1, /**< Instruction (bus) access fault */
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RTE_TRAP_I_ILLEGAL = 2, /**< Illegal instruction */
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RTE_TRAP_BREAKPOINT = 3, /**< Breakpoint (EBREAK instruction) */
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RTE_TRAP_L_MISALIGNED = 4, /**< Load address misaligned */
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RTE_TRAP_L_ACCESS = 5, /**< Load (bus) access fault */
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RTE_TRAP_S_MISALIGNED = 6, /**< Store address misaligned */
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RTE_TRAP_S_ACCESS = 7, /**< Store (bus) access fault */
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RTE_TRAP_MENV_CALL = 8, /**< Environment call from machine mode (ECALL instruction) */
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RTE_TRAP_MSI = 9, /**< Machine software interrupt */
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RTE_TRAP_MTI = 10, /**< Machine timer interrupt */
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RTE_TRAP_MEI = 11, /**< Machine external interrupt */
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RTE_TRAP_FIRQ_0 = 12, /**< Fast interrupt channel 0 */
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RTE_TRAP_FIRQ_1 = 13, /**< Fast interrupt channel 1 */
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RTE_TRAP_FIRQ_2 = 14, /**< Fast interrupt channel 2 */
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RTE_TRAP_FIRQ_3 = 15 /**< Fast interrupt channel 3 */
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};
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// prototypes
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void neorv32_rte_enable_debug_mode(void);
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int neorv32_rte_exception_install(uint8_t exc_id, void (*handler)(void));
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int neorv32_rte_exception_uninstall(uint8_t exc_id);
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void neorv32_rte_setup(void);
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int neorv32_rte_exception_install(uint8_t id, void (*handler)(void));
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int neorv32_rte_exception_uninstall(uint8_t id);
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void neorv32_rte_print_hw_config(void);
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void neorv32_rte_print_hw_version(void);
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@ -43,29 +43,29 @@
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#include "neorv32_rte.h"
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// Privates
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static void __neorv32_rte_dummy_exc_handler(void) __attribute__((unused));
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static uint32_t __neorv32_rte_vector_lut[16] __attribute__((unused)); // trap handler vector table
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static void __attribute__((__interrupt__)) __neorv32_rte_core(void) __attribute__((aligned(16))) __attribute__((unused));
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static void __neorv32_rte_debug_exc_handler(void) __attribute__((unused));
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static void __neorv32_rte_print_true_false(int state) __attribute__((unused));
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/**********************************************************************//**
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* Setup NEORV32 runtime environment in debug mode.
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* Setup NEORV32 runtime environment.
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*
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* @note This function installs a debug handler for ALL exception and interrupt sources, which
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* gives detailed information about the exception/interrupt. Call this function before you
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* install custom handler functions via neorv32_rte_exception_install(uint8_t exc_id, void (*handler)(void)),
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* since this function will override all installed exception handlers.
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*
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* @warning This function should be used for debugging only, since it only shows the uninitialize exception/interrupt, but
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* does not resolve the cause. Hence, it cannot guarantee to resume normal application execution after showing the debug messages.
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* gives detailed information about the exception/interrupt. Actual handler can be installed afterwards
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* via neorv32_rte_exception_install(uint8_t id, void (*handler)(void)).
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**************************************************************************/
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void neorv32_rte_enable_debug_mode(void) {
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void neorv32_rte_setup(void) {
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uint8_t id;
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// configure trap handler base address
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uint32_t mtvec_base = (uint32_t)(&__neorv32_rte_core);
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neorv32_cpu_csr_write(CSR_MTVEC, mtvec_base);
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// install debug handler for all sources
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for (id=0; id<32; id++) {
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neorv32_rte_exception_install(id, __neorv32_rte_debug_exc_handler);
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uint8_t id;
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for (id = 0; id < (sizeof(__neorv32_rte_vector_lut)/sizeof(__neorv32_rte_vector_lut[0])); id++) {
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neorv32_rte_exception_uninstall(id); // this will configure the debug handler
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}
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}
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@ -74,28 +74,32 @@ void neorv32_rte_enable_debug_mode(void) {
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* Install exception handler function to NEORV32 runtime environment.
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*
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* @note This function automatically activates the according CSR.mie bits when installing handlers for
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* the MTIME (MTI), CLIC (MEI) or machine software interrupt (MSI). The global interrupt enable bit mstatus.mie has
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* the MTIME (MTI), CLIC (MEI), machine software interrupt (MSI) or a fast IRQ. The global interrupt enable bit mstatus.mie has
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* to be set by the user via neorv32_cpu_eint(void).
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*
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* @param[in] exc_id Identifier (type) of the targeted exception. See #NEORV32_EXCEPTION_IDS_enum.
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* @param[in] handler The actual handler function for the specified exception (function must be of type "void function(void);").
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* return 0 if success, 1 if error (invalid exc_id or targeted exception not supported).
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* @param[in] id Identifier (type) of the targeted exception. See #NEORV32_RTE_TRAP_enum.
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* @param[in] handler The actual handler function for the specified exception (function MUST be of type "void function(void);").
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* return 0 if success, 1 if error (invalid id or targeted exception not supported).
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**************************************************************************/
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int neorv32_rte_exception_install(uint8_t exc_id, void (*handler)(void)) {
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int neorv32_rte_exception_install(uint8_t id, void (*handler)(void)) {
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// id valid?
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if ((exc_id == EXCID_I_MISALIGNED) || (exc_id == EXCID_I_ACCESS) || (exc_id == EXCID_I_ILLEGAL) ||
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(exc_id == EXCID_BREAKPOINT) || (exc_id == EXCID_L_MISALIGNED) || (exc_id == EXCID_L_ACCESS) ||
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(exc_id == EXCID_S_MISALIGNED) || (exc_id == EXCID_S_ACCESS) || (exc_id == EXCID_MENV_CALL) ||
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(exc_id == EXCID_MSI) || (exc_id == EXCID_MTI) || (exc_id == EXCID_MEI)) {
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if ((id == RTE_TRAP_I_MISALIGNED) || (id == RTE_TRAP_I_ACCESS) || (id == RTE_TRAP_I_ILLEGAL) ||
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(id == RTE_TRAP_BREAKPOINT) || (id == RTE_TRAP_L_MISALIGNED) || (id == RTE_TRAP_L_ACCESS) ||
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(id == RTE_TRAP_S_MISALIGNED) || (id == RTE_TRAP_S_ACCESS) || (id == RTE_TRAP_MENV_CALL) ||
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(id == RTE_TRAP_MSI) || (id == RTE_TRAP_MTI) || (id == RTE_TRAP_MEI) ||
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(id == RTE_TRAP_FIRQ_0) || (id == RTE_TRAP_FIRQ_1) || (id == RTE_TRAP_FIRQ_2) || (id == RTE_TRAP_FIRQ_3)) {
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if (exc_id == EXCID_MSI) { neorv32_cpu_irq_enable(CPU_MIE_MSIE); } // activate software interrupt
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if (exc_id == EXCID_MTI) { neorv32_cpu_irq_enable(CPU_MIE_MTIE); } // activate timer interrupt
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if (exc_id == EXCID_MEI) { neorv32_cpu_irq_enable(CPU_MIE_MEIE); } // activate external interrupt
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uint32_t vt_base = SYSINFO_DSPACE_BASE; // base address of vector table
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vt_base = vt_base + (((uint32_t)exc_id) << 2);
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(*(IO_REG32 (vt_base))) = (uint32_t)handler;
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if (id == RTE_TRAP_MSI) { neorv32_cpu_irq_enable(CPU_MIE_MSIE); } // activate software interrupt
|
||||
if (id == RTE_TRAP_MTI) { neorv32_cpu_irq_enable(CPU_MIE_MTIE); } // activate timer interrupt
|
||||
if (id == RTE_TRAP_MEI) { neorv32_cpu_irq_enable(CPU_MIE_MEIE); } // activate external interrupt
|
||||
if (id == RTE_TRAP_FIRQ_0) { neorv32_cpu_irq_enable(CPU_MIE_FIRQ0E); } // activate fast interrupt channel 0
|
||||
if (id == RTE_TRAP_FIRQ_1) { neorv32_cpu_irq_enable(CPU_MIE_FIRQ1E); } // activate fast interrupt channel 1
|
||||
if (id == RTE_TRAP_FIRQ_2) { neorv32_cpu_irq_enable(CPU_MIE_FIRQ2E); } // activate fast interrupt channel 2
|
||||
if (id == RTE_TRAP_FIRQ_3) { neorv32_cpu_irq_enable(CPU_MIE_FIRQ3E); } // activate fast interrupt channel 3
|
||||
|
||||
__neorv32_rte_vector_lut[id] = (uint32_t)handler; // install handler
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -105,30 +109,33 @@ int neorv32_rte_exception_install(uint8_t exc_id, void (*handler)(void)) {
|
|||
|
||||
/**********************************************************************//**
|
||||
* Uninstall exception handler function from NEORV32 runtime environment, which was
|
||||
* previously installed via neorv32_rte_exception_install(uint8_t exc_id, void (*handler)(void)).
|
||||
* previously installed via neorv32_rte_exception_install(uint8_t id, void (*handler)(void)).
|
||||
*
|
||||
* @note This function automatically clears the according CSR.mie bits when uninstalling handlers for
|
||||
* the MTIME (MTI), CLIC (MEI) or machine software interrupt (MSI). The global interrupt enable bit mstatus.mie has
|
||||
* the MTIME (MTI), CLIC (MEI), machine software interrupt (MSI) or fast IRQs. The global interrupt enable bit mstatus.mie has
|
||||
* to be cleared by the user via neorv32_cpu_dint(void).
|
||||
*
|
||||
* @param[in] exc_id Identifier (type) of the targeted exception. See #NEORV32_EXCEPTION_IDS_enum.
|
||||
* return 0 if success, 1 if error (invalid exc_id or targeted exception not supported).
|
||||
* @param[in] id Identifier (type) of the targeted exception. See #NEORV32_RTE_TRAP_enum.
|
||||
* return 0 if success, 1 if error (invalid id or targeted exception not supported).
|
||||
**************************************************************************/
|
||||
int neorv32_rte_exception_uninstall(uint8_t exc_id) {
|
||||
int neorv32_rte_exception_uninstall(uint8_t id) {
|
||||
|
||||
// id valid?
|
||||
if ((exc_id == EXCID_I_MISALIGNED) || (exc_id == EXCID_I_ACCESS) || (exc_id == EXCID_I_ILLEGAL) ||
|
||||
(exc_id == EXCID_BREAKPOINT) || (exc_id == EXCID_L_MISALIGNED) || (exc_id == EXCID_L_ACCESS) ||
|
||||
(exc_id == EXCID_S_MISALIGNED) || (exc_id == EXCID_S_ACCESS) || (exc_id == EXCID_MENV_CALL) ||
|
||||
(exc_id == EXCID_MSI) || (exc_id == EXCID_MTI) || (exc_id == EXCID_MEI)) {
|
||||
if ((id == RTE_TRAP_I_MISALIGNED) || (id == RTE_TRAP_I_ACCESS) || (id == RTE_TRAP_I_ILLEGAL) ||
|
||||
(id == RTE_TRAP_BREAKPOINT) || (id == RTE_TRAP_L_MISALIGNED) || (id == RTE_TRAP_L_ACCESS) ||
|
||||
(id == RTE_TRAP_S_MISALIGNED) || (id == RTE_TRAP_S_ACCESS) || (id == RTE_TRAP_MENV_CALL) ||
|
||||
(id == RTE_TRAP_MSI) || (id == RTE_TRAP_MTI) || (id == RTE_TRAP_MEI) ||
|
||||
(id == RTE_TRAP_FIRQ_0) || (id == RTE_TRAP_FIRQ_1) || (id == RTE_TRAP_FIRQ_2) || (id == RTE_TRAP_FIRQ_3)) {
|
||||
|
||||
if (exc_id == EXCID_MSI) { neorv32_cpu_irq_disable(CPU_MIE_MSIE); } // deactivate software interrupt
|
||||
if (exc_id == EXCID_MTI) { neorv32_cpu_irq_disable(CPU_MIE_MTIE); } // deactivate timer interrupt
|
||||
if (exc_id == EXCID_MEI) { neorv32_cpu_irq_disable(CPU_MIE_MEIE); } // deactivate external interrupt
|
||||
if (id == RTE_TRAP_MSI) { neorv32_cpu_irq_disable(CPU_MIE_MSIE); } // deactivate software interrupt
|
||||
if (id == RTE_TRAP_MTI) { neorv32_cpu_irq_disable(CPU_MIE_MTIE); } // deactivate timer interrupt
|
||||
if (id == RTE_TRAP_MEI) { neorv32_cpu_irq_disable(CPU_MIE_MEIE); } // deactivate external interrupt
|
||||
if (id == RTE_TRAP_FIRQ_0) { neorv32_cpu_irq_disable(CPU_MIE_FIRQ0E); } // deactivate fast interrupt channel 0
|
||||
if (id == RTE_TRAP_FIRQ_1) { neorv32_cpu_irq_disable(CPU_MIE_FIRQ1E); } // deactivate fast interrupt channel 1
|
||||
if (id == RTE_TRAP_FIRQ_2) { neorv32_cpu_irq_disable(CPU_MIE_FIRQ2E); } // deactivate fast interrupt channel 2
|
||||
if (id == RTE_TRAP_FIRQ_3) { neorv32_cpu_irq_disable(CPU_MIE_FIRQ3E); } // deactivate fast interrupt channel 3
|
||||
|
||||
uint32_t vt_base = SYSINFO_DSPACE_BASE; // base address of vector table
|
||||
vt_base = vt_base + (((uint32_t)exc_id) << 2);
|
||||
(*(IO_REG32 (vt_base))) = (uint32_t)(&__neorv32_rte_dummy_exc_handler); // use dummy handler in case the exception is triggered
|
||||
__neorv32_rte_vector_lut[id] = (uint32_t)(&__neorv32_rte_debug_exc_handler); // use dummy handler in case the exception is accidently triggered
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -137,18 +144,66 @@ int neorv32_rte_exception_uninstall(uint8_t exc_id) {
|
|||
|
||||
|
||||
/**********************************************************************//**
|
||||
* NEORV32 runtime environment: Dummy exception handler (does nothing).
|
||||
* @note This function is used by neorv32_rte_exception_uninstall(uint8_t exc_id) only.
|
||||
* This is the core of the NEORV32 RTE.
|
||||
*
|
||||
* @note This function must no be explicitly used by the user.
|
||||
* @warning When using the the RTE, this function is the ONLY function that can use the 'interrupt' attribute!
|
||||
**************************************************************************/
|
||||
static void __neorv32_rte_dummy_exc_handler(void) {
|
||||
static void __attribute__((__interrupt__)) __attribute__((aligned(16))) __neorv32_rte_core(void) {
|
||||
|
||||
asm volatile("nop");
|
||||
register uint32_t rte_mepc = neorv32_cpu_csr_read(CSR_MEPC);
|
||||
register uint32_t rte_mcause = neorv32_cpu_csr_read(CSR_MCAUSE);
|
||||
|
||||
// compute return address
|
||||
if ((rte_mcause & 0x80000000) == 0) { // modify pc only if exception
|
||||
|
||||
// get low half word of faulting instruction
|
||||
register uint32_t rte_trap_inst;
|
||||
asm volatile ("lh %[result], 0(%[input_i])" : [result] "=r" (rte_trap_inst) : [input_i] "r" (rte_mepc));
|
||||
|
||||
if ((rte_trap_inst & 3) == 3) { // faulting instruction is uncompressed instruction
|
||||
rte_mepc += 4;
|
||||
}
|
||||
else { // faulting instruction is compressed instruction
|
||||
rte_mepc += 2;
|
||||
}
|
||||
|
||||
// store new return address
|
||||
neorv32_cpu_csr_write(CSR_MEPC, rte_mepc);
|
||||
}
|
||||
|
||||
// find according trap handler
|
||||
register uint32_t rte_handler = (uint32_t)(&__neorv32_rte_debug_exc_handler);
|
||||
switch (rte_mcause) {
|
||||
case TRAP_CODE_I_MISALIGNED: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_I_MISALIGNED]; break;
|
||||
case TRAP_CODE_I_ACCESS: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_I_ACCESS]; break;
|
||||
case TRAP_CODE_I_ILLEGAL: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_I_ILLEGAL]; break;
|
||||
case TRAP_CODE_BREAKPOINT: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_BREAKPOINT]; break;
|
||||
case TRAP_CODE_L_MISALIGNED: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_L_MISALIGNED]; break;
|
||||
case TRAP_CODE_L_ACCESS: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_L_ACCESS]; break;
|
||||
case TRAP_CODE_S_MISALIGNED: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_S_MISALIGNED]; break;
|
||||
case TRAP_CODE_S_ACCESS: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_S_ACCESS]; break;
|
||||
case TRAP_CODE_MENV_CALL: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_MENV_CALL]; break;
|
||||
case TRAP_CODE_MSI: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_MSI]; break;
|
||||
case TRAP_CODE_MTI: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_MTI]; break;
|
||||
case TRAP_CODE_MEI: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_MEI]; break;
|
||||
case TRAP_CODE_FIRQ_0: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_0]; break;
|
||||
case TRAP_CODE_FIRQ_1: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_1]; break;
|
||||
case TRAP_CODE_FIRQ_2: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_2]; break;
|
||||
case TRAP_CODE_FIRQ_3: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_3]; break;
|
||||
default: break;
|
||||
}
|
||||
|
||||
// execute handler
|
||||
void (*handler_pnt)(void);
|
||||
handler_pnt = (void*)rte_handler;
|
||||
(*handler_pnt)();
|
||||
}
|
||||
|
||||
|
||||
/**********************************************************************//**
|
||||
* NEORV32 runtime environment: Debug exception handler, printing various exception/interrupt information via UART.
|
||||
* @note This function is used by neorv32_rte_enable_debug_mode(void) only.
|
||||
* @note This function is used by neorv32_rte_exception_uninstall(void) only.
|
||||
**************************************************************************/
|
||||
static void __neorv32_rte_debug_exc_handler(void) {
|
||||
|
||||
|
|
@ -179,29 +234,34 @@ static void __neorv32_rte_debug_exc_handler(void) {
|
|||
|
||||
neorv32_uart_printf("Cause: ");
|
||||
switch (trap_cause) {
|
||||
case 0x00000000: neorv32_uart_printf("Instruction address misaligned"); break;
|
||||
case 0x00000001: neorv32_uart_printf("Instruction access fault"); break;
|
||||
case 0x00000002: neorv32_uart_printf("Illegal instruction"); break;
|
||||
case 0x00000003: neorv32_uart_printf("Breakpoint (EBREAK)"); break;
|
||||
case 0x00000004: neorv32_uart_printf("Load address misaligned"); break;
|
||||
case 0x00000005: neorv32_uart_printf("Load access fault"); break;
|
||||
case 0x00000006: neorv32_uart_printf("Store address misaligned"); break;
|
||||
case 0x00000007: neorv32_uart_printf("Store access fault"); break;
|
||||
case 0x0000000B: neorv32_uart_printf("Environment call (ECALL)"); break;
|
||||
case 0x80000003: neorv32_uart_printf("Machine software interrupt"); break;
|
||||
case 0x80000007: neorv32_uart_printf("Machine timer interrupt (via MTIME)"); break;
|
||||
case 0x8000000B: neorv32_uart_printf("Machine external interrupt (via CLIC)"); break;
|
||||
default: neorv32_uart_printf("Unknown (0x%x)", trap_cause); break;
|
||||
case TRAP_CODE_I_MISALIGNED: neorv32_uart_printf("Instruction address misaligned"); break;
|
||||
case TRAP_CODE_I_ACCESS: neorv32_uart_printf("Instruction access fault"); break;
|
||||
case TRAP_CODE_I_ILLEGAL: neorv32_uart_printf("Illegal instruction"); break;
|
||||
case TRAP_CODE_BREAKPOINT: neorv32_uart_printf("Breakpoint (EBREAK)"); break;
|
||||
case TRAP_CODE_L_MISALIGNED: neorv32_uart_printf("Load address misaligned"); break;
|
||||
case TRAP_CODE_L_ACCESS: neorv32_uart_printf("Load access fault"); break;
|
||||
case TRAP_CODE_S_MISALIGNED: neorv32_uart_printf("Store address misaligned"); break;
|
||||
case TRAP_CODE_S_ACCESS: neorv32_uart_printf("Store access fault"); break;
|
||||
case TRAP_CODE_MENV_CALL: neorv32_uart_printf("Environment call from M-mode"); break;
|
||||
case TRAP_CODE_MSI: neorv32_uart_printf("Machine software interrupt"); break;
|
||||
case TRAP_CODE_MTI: neorv32_uart_printf("Machine timer interrupt"); break;
|
||||
case TRAP_CODE_MEI: neorv32_uart_printf("Machine external interrupt"); break;
|
||||
case TRAP_CODE_FIRQ_0: neorv32_uart_printf("Fast interrupt channel 0"); break;
|
||||
case TRAP_CODE_FIRQ_1: neorv32_uart_printf("Fast interrupt channel 1"); break;
|
||||
case TRAP_CODE_FIRQ_2: neorv32_uart_printf("Fast interrupt channel 2"); break;
|
||||
case TRAP_CODE_FIRQ_3: neorv32_uart_printf("Fast interrupt channel 3"); break;
|
||||
default: neorv32_uart_printf("Unknown (0x%x)", trap_cause); break;
|
||||
}
|
||||
|
||||
// fault address
|
||||
neorv32_uart_printf("\nFaulting instruction (low): 0x%x\n", trap_inst);
|
||||
neorv32_uart_printf("MTVAL: 0x%x\n", neorv32_cpu_csr_read(CSR_MTVAL));
|
||||
neorv32_uart_printf("\nFaulting instruction (low half word): 0x%x", trap_inst);
|
||||
|
||||
if ((trap_inst & 3) != 3) {
|
||||
neorv32_uart_printf("(decompressed)\n");
|
||||
neorv32_uart_printf(" (decompressed)\n");
|
||||
}
|
||||
|
||||
neorv32_uart_printf("\nMTVAL: 0x%x\n", neorv32_cpu_csr_read(CSR_MTVAL));
|
||||
|
||||
neorv32_uart_printf("Trying to resume application @ 0x%x...", neorv32_cpu_csr_read(CSR_MEPC));
|
||||
|
||||
neorv32_uart_printf("\n<</NEORV32 Runtime Environment >>\n\n");
|
||||
|
|
@ -313,9 +373,6 @@ void neorv32_rte_print_hw_config(void) {
|
|||
neorv32_uart_printf("WDT: ");
|
||||
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_WDT));
|
||||
|
||||
neorv32_uart_printf("CLIC: ");
|
||||
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_CLIC));
|
||||
|
||||
neorv32_uart_printf("TRNG: ");
|
||||
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_TRNG));
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue