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[trng] comment fix

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stnolting 2023-11-05 18:07:05 +01:00
parent c117b2d016
commit 141a513e2d
1 changed files with 4 additions and 3 deletions
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7
rtl/core/neorv32_trng.vhd
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@ -244,9 +244,10 @@ end neorv32_trng_rtl;
-- # can be implemented for any FPGA without requiring primitive instantiation or technology- #
-- # specific attributes or synthesis options. #
-- # #
-- # The random output from all entropy cells is synchronized, XOR-ed and fed to a simple 2-bit a #
-- # von Neumann randomness extractor (extracting edges). 64 de-biased bits are "combined" using a #
-- # LFSR-style shift register to provide one random data byte. #
-- # The random output from each entropy cells is synchronized and XOR-ed with the other cell's #
-- # outputs before it is and fed into a simple 2-bit "von Neumann randomness extractor" #
-- # (extracting edges). 64 de-biased bits are "combined" using a LFSR-style shift register (in #
-- # order to improve spectral distribution) to provide one final random data byte. #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #