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adjust SPI control register bits

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stnolting 2023-03-04 17:46:14 +01:00
parent 52a826f022
commit 146fca3bf3
4 changed files with 30 additions and 32 deletions
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19
docs/datasheet/soc_spi.adoc
View file

@ -116,22 +116,21 @@ Furthermore, an active SPI interrupt has to be explicitly cleared again by writi
[options="header",grid="all"]
|=======================
| Address | Name [C] | Bit(s), Name [C] | R/W | Function
.16+<| `0xffffffa8` .19+<| `CTRL` <|`0` _SPI_CTRL_EN_ ^| r/w <| SPI module enable
.16+<| `0xffffffa8` .18+<| `CTRL` <|`0` _SPI_CTRL_EN_ ^| r/w <| SPI module enable
<|`1` _SPI_CTRL_CPHA_ ^| r/w <| clock phase
<|`2` _SPI_CTRL_CPOL_ ^| r/w <| clock polarity
<|`5:3` _SPI_CTRL_CS_SEL2_ : _SPI_CTRL_CS_SEL0_ ^| r/w <| Direct chip-select 0..7
<|`6` _SPI_CTRL_CS_EN_ ^| r/w <| Direct chip-select enable: setting `spi_csn_o(SPI_CTRL_CS_SEL)` low when set
<|`9:7` _SPI_CTRL_PRSC2_ : _SPI_CTRL_PRSC0_ ^| r/w <| 3-bit clock prescaler select
<|`13:10` _SPI_CTRL_CDIV2_ : _SPI_CTRL_CDIV0_ ^| r/w <| 4-bit clock divider
<|`14` _reserved_ ^| r/- <| reserved, read as zero
<|`15` _SPI_CTRL_RX_AVAIL_ ^| r/- <| RX FIFO data available (RX FIFO not empty)
<|`16` _SPI_CTRL_TX_EMPTY_ ^| r/- <| TX FIFO empty
<|`17` _SPI_CTRL_TX_NHALF_ ^| r/- <| TX FIFO _not_ at least half full
<|`18` _SPI_CTRL_TX_FULL_ ^| r/- <| TX FIFO full
<|`19` _SPI_CTRL_IRQ_RX_AVAIL_ ^| r/w <| Trigger IRQ if RX FIFO not empty
<|`20` _SPI_CTRL_IRQ_TX_EMPTY_ ^| r/w <| Trigger IRQ if TX FIFO empty
<|`21` _SPI_CTRL_IRQ_TX_NHALF_ ^| r/w <| Trigger IRQ if TX FIFO _not_ at least half full
<|`22` _reserved_ ^| r/- <| reserved, read as zero
<|`15:14` _reserved_ ^| r/- <| reserved, read as zero
<|`16` _SPI_CTRL_RX_AVAIL_ ^| r/- <| RX FIFO data available (RX FIFO not empty)
<|`17` _SPI_CTRL_TX_EMPTY_ ^| r/- <| TX FIFO empty
<|`18` _SPI_CTRL_TX_NHALF_ ^| r/- <| TX FIFO _not_ at least half full
<|`19` _SPI_CTRL_TX_FULL_ ^| r/- <| TX FIFO full
<|`20` _SPI_CTRL_IRQ_RX_AVAIL_ ^| r/w <| Trigger IRQ if RX FIFO not empty
<|`21` _SPI_CTRL_IRQ_TX_EMPTY_ ^| r/w <| Trigger IRQ if TX FIFO empty
<|`22` _SPI_CTRL_IRQ_TX_NHALF_ ^| r/w <| Trigger IRQ if TX FIFO _not_ at least half full
<|`26:23` _SPI_CTRL_FIFO_MSB_ : _SPI_CTRL_FIFO_LSB_ ^| r/- <| FIFO depth; log2(_IO_SPI_FIFO_)
<|`30:27` _reserved_ ^| r/- <| reserved, read as zero
<|`31` _SPI_CTRL_BUSY_ ^| r/- <| SPI module busy when set (serial engine operation in progress and TX FIFO not empty yet)

15
rtl/core/neorv32_spi.vhd
View file

@ -88,14 +88,13 @@ architecture neorv32_spi_rtl of neorv32_spi is
constant ctrl_cdiv2_c : natural := 12; -- r/w: clock divider bit 2
constant ctrl_cdiv3_c : natural := 13; -- r/w: clock divider bit 3
--
constant ctrl_rx_avail_c : natural := 15; -- r/-: rx fifo data available (fifo not empty)
constant ctrl_tx_empty_c : natural := 16; -- r/-: tx fifo empty
constant ctrl_tx_nhalf_c : natural := 17; -- r/-: tx fifo not at least half full
constant ctrl_tx_full_c : natural := 18; -- r/-: tx fifo full
constant ctrl_irq_rx_avail_c : natural := 19; -- r/w: fire irq if rx fifo data available (fifo not empty)
constant ctrl_irq_tx_empty_c : natural := 20; -- r/w: fire irq if tx fifo empty
constant ctrl_irq_tx_nhalf_c : natural := 21; -- r/w: fire irq if tx fifo not at least half full
--
constant ctrl_rx_avail_c : natural := 16; -- r/-: rx fifo data available (fifo not empty)
constant ctrl_tx_empty_c : natural := 17; -- r/-: tx fifo empty
constant ctrl_tx_nhalf_c : natural := 18; -- r/-: tx fifo not at least half full
constant ctrl_tx_full_c : natural := 19; -- r/-: tx fifo full
constant ctrl_irq_rx_avail_c : natural := 20; -- r/w: fire irq if rx fifo data available (fifo not empty)
constant ctrl_irq_tx_empty_c : natural := 21; -- r/w: fire irq if tx fifo empty
constant ctrl_irq_tx_nhalf_c : natural := 22; -- r/w: fire irq if tx fifo not at least half full
constant ctrl_fifo_size0_c : natural := 23; -- r/-: log2(fifo size), bit 0 (lsb)
constant ctrl_fifo_size1_c : natural := 24; -- r/-: log2(fifo size), bit 1
constant ctrl_fifo_size2_c : natural := 25; -- r/-: log2(fifo size), bit 2

14
sw/lib/include/neorv32.h
View file

@ -1082,14 +1082,14 @@ enum NEORV32_SPI_CTRL_enum {
SPI_CTRL_CDIV2 = 12, /**< SPI control register(12) (r/w): Clock divider bit 2 */
SPI_CTRL_CDIV3 = 13, /**< SPI control register(13) (r/w): Clock divider bit 3 */
SPI_CTRL_RX_AVAIL = 15, /**< SPI control register(15) (r/-): RX FIFO data available (RX FIFO not empty) */
SPI_CTRL_TX_EMPTY = 16, /**< SPI control register(16) (r/-): TX FIFO empty */
SPI_CTRL_TX_NHALF = 17, /**< SPI control register(17) (r/-): TX FIFO not at least half full */
SPI_CTRL_TX_FULL = 18, /**< SPI control register(18) (r/-): TX FIFO full */
SPI_CTRL_RX_AVAIL = 16, /**< SPI control register(16) (r/-): RX FIFO data available (RX FIFO not empty) */
SPI_CTRL_TX_EMPTY = 17, /**< SPI control register(17) (r/-): TX FIFO empty */
SPI_CTRL_TX_NHALF = 18, /**< SPI control register(18) (r/-): TX FIFO not at least half full */
SPI_CTRL_TX_FULL = 19, /**< SPI control register(19) (r/-): TX FIFO full */
SPI_CTRL_IRQ_RX_AVAIL = 19, /**< SPI control register(19) (r/w): Fire IRQ if RX FIFO data available (RX FIFO not empty) */
SPI_CTRL_IRQ_TX_EMPTY = 20, /**< SPI control register(20) (r/w): Fire IRQ if TX FIFO empty */
SPI_CTRL_IRQ_TX_HALF = 21, /**< SPI control register(21) (r/w): Fire IRQ if TX FIFO not at least half full */
SPI_CTRL_IRQ_RX_AVAIL = 20, /**< SPI control register(20) (r/w): Fire IRQ if RX FIFO data available (RX FIFO not empty) */
SPI_CTRL_IRQ_TX_EMPTY = 21, /**< SPI control register(21) (r/w): Fire IRQ if TX FIFO empty */
SPI_CTRL_IRQ_TX_HALF = 22, /**< SPI control register(22) (r/w): Fire IRQ if TX FIFO not at least half full */
SPI_CTRL_FIFO_LSB = 23, /**< SPI control register(23) (r/-): log2(FIFO size), lsb */
SPI_CTRL_FIFO_MSB = 26, /**< SPI control register(26) (r/-): log2(FIFO size), msb */

14
sw/svd/neorv32.svd
View file

@ -847,41 +847,41 @@
</field>
<field>
<name>SPI_CTRL_RX_AVAIL</name>
<bitRange>[15:15]</bitRange>
<bitRange>[16:16]</bitRange>
<access>read-only</access>
<description>RX FIFO data available (RX FIFO not empty)</description>
</field>
<field>
<name>SPI_CTRL_TX_EMPTY</name>
<bitRange>[16:16]</bitRange>
<bitRange>[17:17]</bitRange>
<access>read-only</access>
<description>TX FIFO is empty</description>
</field>
<field>
<name>SPI_CTRL_TX_NHALF</name>
<bitRange>[17:17]</bitRange>
<bitRange>[18:18]</bitRange>
<access>read-only</access>
<description>TX FIFO not at least half full</description>
</field>
<field>
<name>SPI_CTRL_TX_FULL</name>
<bitRange>[18:18]</bitRange>
<bitRange>[19:19]</bitRange>
<access>read-only</access>
<description>TX FIFO is full</description>
</field>
<field>
<name>SPI_CTRL_IRQ_RX_AVAIL</name>
<bitRange>[19:19]</bitRange>
<bitRange>[20:20]</bitRange>
<description>Fire interrupt if RX FIFO is not empty</description>
</field>
<field>
<name>SPI_CTRL_IRQ_TX_EMPTY</name>
<bitRange>[20:20]</bitRange>
<bitRange>[21:21]</bitRange>
<description>Fire interrupt if TX FIFO is empty</description>
</field>
<field>
<name>SPI_CTRL_IRQ_TX_NHALF</name>
<bitRange>[21:21]</bitRange>
<bitRange>[22:22]</bitRange>
<description>Fire interrupt if TX FIFO is not at least half full</description>
</field>
<field>