[rtl] add 'Zicond' ISA extension's co-processor

2025-04-23 21:57:33 -04:00 · 2023-02-23 18:27:33 +01:00 · 2023-02-23 18:27:33 +01:00 · 14f1b50e26
commit 14f1b50e26
parent ca00e1e23f
1 changed files with 89 additions and 0 deletions
--- a/rtl/core/neorv32_cpu_cp_cond.vhd
+++ b/rtl/core/neorv32_cpu_cp_cond.vhd
@ -0,0 +1,89 @@
+-- #################################################################################################
+-- # << NEORV32 - CPU Co-Processor: RISC-V Conditional Operations ('Zicond') ISA Extension >>      #
+-- # ********************************************************************************************* #
+-- # BSD 3-Clause License                                                                          #
+-- #                                                                                               #
+-- # Copyright (c) 2023, Stephan Nolting. All rights reserved.                                     #
+-- #                                                                                               #
+-- # Redistribution and use in source and binary forms, with or without modification, are          #
+-- # permitted provided that the following conditions are met:                                     #
+-- #                                                                                               #
+-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #
+-- #    conditions and the following disclaimer.                                                   #
+-- #                                                                                               #
+-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
+-- #    conditions and the following disclaimer in the documentation and/or other materials        #
+-- #    provided with the distribution.                                                            #
+-- #                                                                                               #
+-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
+-- #    endorse or promote products derived from this software without specific prior written      #
+-- #    permission.                                                                                #
+-- #                                                                                               #
+-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
+-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
+-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
+-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
+-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
+-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
+-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
+-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
+-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
+-- # ********************************************************************************************* #
+-- # The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32       (c) Stephan Nolting #
+-- #################################################################################################
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library neorv32;
+use neorv32.neorv32_package.all;
+
+entity neorv32_cpu_cp_cond is
+  generic (
+    XLEN : natural -- data path width
+  );
+  port (
+    -- global control --
+    clk_i   : in  std_ulogic; -- global clock, rising edge
+    ctrl_i  : in  ctrl_bus_t; -- main control bus
+    start_i : in  std_ulogic; -- trigger operation
+    -- data input --
+    rs1_i   : in  std_ulogic_vector(XLEN-1 downto 0); -- rf source 1
+    rs2_i   : in  std_ulogic_vector(XLEN-1 downto 0); -- rf source 2
+    -- result and status --
+    res_o   : out std_ulogic_vector(XLEN-1 downto 0); -- operation result
+    valid_o : out std_ulogic -- data output valid
+  );
+end neorv32_cpu_cp_cond;
+
+architecture neorv32_cpu_cp_cond_rtl of neorv32_cpu_cp_cond is
+
+  constant zero_c : std_ulogic_vector(XLEN-1 downto 0) := (others => '0');
+  signal rs2_zero, condition : std_ulogic;
+
+begin
+
+  -- Compliance notifier --
+  assert (true) report "NEORV32 PROCESSOR CONFIG WARNING: The RISC-V 'Zicond' ISA extension is neither ratified nor frozen (yet)." severity warning;
+
+  -- Conditional output --
+  process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      res_o <= (others => '0'); -- default
+      if (start_i = '1') and (condition = '1') then
+        res_o <= rs1_i;
+      end if;
+    end if;
+  end process;
+
+  -- condition check --
+  rs2_zero  <= '1' when (rs2_i = zero_c) else '0';
+  condition <= rs2_zero xnor ctrl_i.ir_funct3(1); -- equal zero / non equal zero
+
+  -- processing done --
+  valid_o <= start_i;
+
+
+end neorv32_cpu_cp_cond_rtl;