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[docs] update IO module base addresses

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stnolting 2023-07-16 21:03:15 +02:00
parent 951fc1c153
commit 165c88a6d3
19 changed files with 63 additions and 63 deletions
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12
docs/datasheet/on_chip_debugger.adoc
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@ -414,14 +414,14 @@ the _program buffer_, the _data buffer_ and the _status register_. The program b
status register do not fully occupy the 64-byte-wide sections and are mirrored to fill the entire section.
.DM CPU access - address map (divided into four sections)
[cols="^2,^4,^2,<7"]
[cols="^2,^2,<5"]
[options="header",grid="rows"]
|=======================
| Base address | Name [VHDL package] | Actual size | Description
| `0xfffff800` | `dm_code_base_c` (= `dm_base_c`) | 64 bytes | ROM for the "park loop" code
| `0xfffff840` | `dm_pbuf_base_c` | 16 bytes | Program buffer, provided by DM
| `0xfffff880` | `dm_data_base_c` | 4 bytes | Data buffer (`dm.data0`)
| `0xfffff8c0` | `dm_sreg_base_c` | 4 bytes | Control and status register
| Base address | Actual size | Description
| `0xffffff00` | 64 bytes | ROM for the "park loop" code
| `0xffffff40` | 16 bytes | Program buffer, provided by DM
| `0xffffff80` | 4 bytes | Data buffer (`dm.data0`)
| `0xffffffc0` | 4 bytes | Control and status register
|=======================
.DM Register Access

8
docs/datasheet/soc_cfs.adoc
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@ -93,9 +93,9 @@ generic (default = 32-bit). The size of the output signal conduit `cfs_out_o` is
[options="header",grid="all"]
|=======================
| Address | Name [C] | Bit(s) | R/W | Function
| `0xfffffe00` | `REG[0]` |`31:0` | (r)/(w) | custom CFS register 0
| `0xfffffe04` | `REG[1]` |`31:0` | (r)/(w) | custom CFS register 1
| `0xffffeb00` | `REG[0]` |`31:0` | (r)/(w) | custom CFS register 0
| `0xffffeb04` | `REG[1]` |`31:0` | (r)/(w) | custom CFS register 1
| ... | ... |`31:0` | (r)/(w) | ...
| `0xfffffef8` | `REG[62]` |`31:0` | (r)/(w) | custom CFS register 62
| `0xfffffefc` | `REG[63]` |`31:0` | (r)/(w) | custom CFS register 63
| `0xffffebf8` | `REG[62]` |`31:0` | (r)/(w) | custom CFS register 62
| `0xffffebfc` | `REG[63]` |`31:0` | (r)/(w) | custom CFS register 63
|=======================

8
docs/datasheet/soc_crc.adoc
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@ -62,10 +62,10 @@ and for CRC32-mode the entire 32-bit of `POLY` and `SREG` are used.
[options="header",grid="all"]
|=======================
| Address | Name [C] | Bit(s), Name [C] | R/W | Function
.2+<| `0xffffff20` .2+<| `CTRL` <|`1:0` ^| r/w <| CRC mode select (`00` CRC8, `01`: CRC16, `10`: CRC32)
.2+<| `0xffffee00` .2+<| `CTRL` <|`1:0` ^| r/w <| CRC mode select (`00` CRC8, `01`: CRC16, `10`: CRC32)
<|`31:2` ^| r/- <| _reserved_, read as zero
| `0xffffff24` | `POLY` |`31:0` | r/w | CRC polynomial
.2+<| `0xffffff28` .2+<| `DATA` <|`7:0` ^| r/w <| data input (single byte)
| `0xffffee04` | `POLY` |`31:0` | r/w | CRC polynomial
.2+<| `0xffffee08` .2+<| `DATA` <|`7:0` ^| r/w <| data input (single byte)
<|`31:8` ^| r/- <| _reserved_, read as zero, writes are ignored
| `0xffffff2c` | `SREG` |`32:0` | r/w | current CRC shift register value (set start value on write)
| `0xffffee0c` | `SREG` |`32:0` | r/w | current CRC shift register value (set start value on write)
|=======================

8
docs/datasheet/soc_dma.adoc
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@ -122,7 +122,7 @@ explicitly cleared again by writing zero to the according <<_mip>> CSR bit.
[options="header",grid="all"]
|=======================
| Address | Name [C] | Bit(s), Name [C] | R/W | Function
.8+<| `0xffffff10` .8+<| `CTRL` <|`0` `DMA_CTRL_EN` ^| r/w <| DMA module enable
.8+<| `0xffffed00` .8+<| `CTRL` <|`0` `DMA_CTRL_EN` ^| r/w <| DMA module enable
<|`1` `DMA_CTRL_AUTO` ^| r/w <| Enable automatic mode (FIRQ-triggered)
<|`7:2` _reserved_ ^| r/- <| reserved, read as zero
<|`8` `DMA_CTRL_ERROR_RD` ^| r/- <| Error during read access, clears when starting a new transfer
@ -130,9 +130,9 @@ explicitly cleared again by writing zero to the according <<_mip>> CSR bit.
<|`10` `DMA_CTRL_BUSY` ^| r/- <| DMA transfer in progress
<|`15:11` _reserved_ ^| r/- <| reserved, read as zero
<|`31:16` `DMA_CTRL_FIRQ_MASK_MSB : DMA_CTRL_FIRQ_MASK_LSB` ^| r/w <| FIRQ trigger mask (same bits as in <<_mip>>)
| `0xffffff14` | `SRC_BASE` |`31:0` | r/w | Source base address (shows the last-accessed source address when read)
| `0xffffff18` | `DST_BASE` |`31:0` | r/w | Destination base address (shows the last-accessed destination address when read)
.6+<| `0xffffff1c` .6+<| `TTYPE` <|`23:0` `DMA_TTYPE_NUM_MSB : DMA_TTYPE_NUM_LSB` ^| r/w <| Number of elements to transfer (shows the last-transferred element index when read)
| `0xffffed04` | `SRC_BASE` |`31:0` | r/w | Source base address (shows the last-accessed source address when read)
| `0xffffed08` | `DST_BASE` |`31:0` | r/w | Destination base address (shows the last-accessed destination address when read)
.6+<| `0xffffed0c` .6+<| `TTYPE` <|`23:0` `DMA_TTYPE_NUM_MSB : DMA_TTYPE_NUM_LSB` ^| r/w <| Number of elements to transfer (shows the last-transferred element index when read)
<|`26:24` _reserved_ ^| r/- <| reserved, read as zero
<|`28:27` `DMA_TTYPE_QSEL_MSB : DMA_TTYPE_QSEL_LSB` ^| r/w <| Source data quantity select (`00` = byte, `01` = half-word, `10` = word)
<|`29` `DMA_TTYPE_SRC_INC` ^| r/w <| Constant (`0`) or incrementing (`1`) source address

8
docs/datasheet/soc_gpio.adoc
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@ -37,8 +37,8 @@ be performed within a single clock cycle.
[options="header",grid="rows"]
|=======================
| Address | Name [C] | Bit(s) | R/W | Function
| `0xffffffc0` | `INPUT_LO` | 31:0 | r/- | parallel input port pins 31:0
| `0xffffffc4` | `INPUT_HI` | 31:0 | r/- | parallel input port pins 63:32
| `0xffffffc8` | `OUTPUT_LO` | 31:0 | r/w | parallel output port pins 31:0
| `0xffffffcc` | `OUTPUT_HI` | 31:0 | r/w | parallel output port pins 63:32
| `0xfffffc00` | `INPUT_LO` | 31:0 | r/- | parallel input port pins 31:0
| `0xfffffc04` | `INPUT_HI` | 31:0 | r/- | parallel input port pins 63:32
| `0xfffffc08` | `OUTPUT_LO` | 31:0 | r/w | parallel output port pins 31:0
| `0xfffffc0c` | `OUTPUT_HI` | 31:0 | r/w | parallel output port pins 63:32
|=======================

6
docs/datasheet/soc_gptmr.adoc
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@ -57,10 +57,10 @@ remains pending inside the CPU until it explicitly cleared by writing zero to th
[options="header",grid="all"]
|=======================
| Address | Name [C] | Bit(s), Name [C] | R/W | Function
.4+<| `0xffffff60` .4+<| `CTRL` <|`0` `GPTMR_CTRL_EN` ^| r/w <| Timer enable flag
.4+<| `0xfffff100` .4+<| `CTRL` <|`0` `GPTMR_CTRL_EN` ^| r/w <| Timer enable flag
<|`3:1` `GPTMR_CTRL_PRSC2 : GPTMR_CTRL_PRSC0` ^| r/w <| 3-bit clock prescaler select
<|`4` `GPTMR_CTRL_MODE` ^| r/w <| Counter mode: `0`=single-shot, `1`=continuous
<|`31:5` - ^| r/- <| _reserved_, read as zero
| `0xffffff64` | `THRES` |`31:0` | r/w | Threshold value register
| `0xffffff68` | `COUNT` |`31:0` | r/w | Counter register
| `0xfffff104` | `THRES` |`31:0` | r/w | Threshold value register
| `0xfffff108` | `COUNT` |`31:0` | r/w | Counter register
|=======================

8
docs/datasheet/soc_mtime.adoc
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@ -39,8 +39,8 @@ the interrupt request is explicitly acknowledged (e.g. writing to a memory-mappe
[options="header",grid="all"]
|=======================
| Address | Name [C] | Bits | R/W | Function
| `0xffffff90` | `TIME_LO` | 31:0 | r/w | machine system time, low word
| `0xffffff94` | `TIME_HI` | 31:0 | r/w | machine system time, high word
| `0xffffff98` | `TIMECMP_LO` | 31:0 | r/w | time compare, low word
| `0xffffff9c` | `TIMECMP_HI` | 31:0 | r/w | time compare, high word
| `0xfffff400` | `TIME_LO` | 31:0 | r/w | machine system time, low word
| `0xfffff404` | `TIME_HI` | 31:0 | r/w | machine system time, high word
| `0xfffff408` | `TIMECMP_LO` | 31:0 | r/w | time compare, low word
| `0xfffff40c` | `TIMECMP_HI` | 31:0 | r/w | time compare, high word
|=======================

4
docs/datasheet/soc_neoled.adoc
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@ -186,7 +186,7 @@ writing zero to according <<_mip>> CSR bit.
[options="header",grid="all"]
|=======================
| Address | Name [C] | Bit(s), Name [C] | R/W | Function
.13+<| `0xffffffd8` .13+<| `CTRL` <|`0` `NEOLED_CTRL_EN` ^| r/w <| NEOLED enable
.13+<| `0xfffffd00` .13+<| `CTRL` <|`0` `NEOLED_CTRL_EN` ^| r/w <| NEOLED enable
<|`1` `NEOLED_CTRL_MODE` ^| r/w <| data transfer size; `0`=24-bit; `1`=32-bit
<|`2` `NEOLED_CTRL_STROBE` ^| r/w <| `0`=send normal color data; `1`=send RESET command on data write access
<|`5:3` `NEOLED_CTRL_PRSC2 : NEOLED_CTRL_PRSC0` ^| r/w <| 3-bit clock prescaler, bit 0
@ -199,5 +199,5 @@ writing zero to according <<_mip>> CSR bit.
<|`29` `NEOLED_CTRL_TX_HALF` ^| r/- <| TX FIFO is _at least_ half full
<|`30` `NEOLED_CTRL_TX_FULL` ^| r/- <| TX FIFO is full
<|`31` `NEOLED_CTRL_TX_BUSY` ^| r/- <| TX serial engine is busy when set
| `0xffffffdc` | `DATA` <|`31:0` / `23:0` ^| -/w <| TX data (32- or 24-bit, depending on _NEOLED_CTRL_MODE_ bit)
| `0xfffffd04` | `DATA` <|`31:0` / `23:0` ^| -/w <| TX data (32- or 24-bit, depending on _NEOLED_CTRL_MODE_ bit)
|=======================

4
docs/datasheet/soc_onewire.adoc
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@ -176,7 +176,7 @@ according <<_mip>> CSR FIRQ bit.
[options="header",grid="all"]
|=======================
| Address | Name [C] | Bit(s), Name [C] | R/W | Function
.10+<| `0xffffff70` .10+<| `CTRL` <|`0` `ONEWIRE_CTRL_EN` ^| r/w <| ONEWIRE enable, reset if cleared
.10+<| `0xfffff200` .10+<| `CTRL` <|`0` `ONEWIRE_CTRL_EN` ^| r/w <| ONEWIRE enable, reset if cleared
<|`2:1` `ONEWIRE_CTRL_PRSC1 : ONEWIRE_CTRL_PRSC0` ^| r/w <| 2-bit clock prescaler select
<|`10:3` `ONEWIRE_CTRL_CLKDIV7 : ONEWIRE_CTRL_CLKDIV0` ^| r/w <| 8-bit clock divider value
<|`11` `ONEWIRE_CTRL_TRIG_RST` ^| -/w <| trigger reset pulse, auto-clears
@ -186,5 +186,5 @@ according <<_mip>> CSR FIRQ bit.
<|`29` `ONEWIRE_CTRL_SENSE` ^| r/- <| current state of the bus line
<|`30` `ONEWIRE_CTRL_PRESENCE` ^| r/- <| device presence detected after reset pulse
<|`31` `ONEWIRE_CTRL_BUSY` ^| r/- <| operation in progress when set
| `0xffffff74` | `DATA` |`7:0` `ONEWIRE_DATA_MSB : ONEWIRE_DATA_LSB` | r/w | receive/transmit data (8-bit)
| `0xfffff204` | `DATA` |`7:0` `ONEWIRE_DATA_MSB : ONEWIRE_DATA_LSB` | r/w | receive/transmit data (8-bit)
|=======================

8
docs/datasheet/soc_pwm.adoc
View file

@ -67,18 +67,18 @@ _**f~PWM~**_ = _f~main~[Hz]_ / (2^8^ * `clock_prescaler`)
[options="header",grid="all"]
|=======================
| Address | Name [C] | Bit(s), Name [C] | R/W | Function
.3+<| `0xffffff50` .3+<| `CTRL` <|`0` `PWM_CTRL_EN` ^| r/w <| PWM enable
.3+<| `0xfffff000` .3+<| `CTRL` <|`0` `PWM_CTRL_EN` ^| r/w <| PWM enable
<|`3:1` `PWM_CTRL_PRSC2 : PWM_CTRL_PRSC0` ^| r/w <| 3-bit clock prescaler select
<|`31:4` - ^| r/- <| _reserved_, read as zero
.4+<| `0xffffff54` .4+<| `DC[0]` <|`7:0` ^| r/w <| 8-bit duty cycle for channel 0
.4+<| `0xfffff004` .4+<| `DC[0]` <|`7:0` ^| r/w <| 8-bit duty cycle for channel 0
<|`15:8` ^| r/w <| 8-bit duty cycle for channel 1
<|`23:16` ^| r/w <| 8-bit duty cycle for channel 2
<|`31:24` ^| r/w <| 8-bit duty cycle for channel 3
.4+<| `0xffffff58` .4+<| `DC[1]` <|`7:0` ^| r/w <| 8-bit duty cycle for channel 4
.4+<| `0xfffff008` .4+<| `DC[1]` <|`7:0` ^| r/w <| 8-bit duty cycle for channel 4
<|`15:8` ^| r/w <| 8-bit duty cycle for channel 5
<|`23:16` ^| r/w <| 8-bit duty cycle for channel 6
<|`31:24` ^| r/w <| 8-bit duty cycle for channel 7
.4+<| `0xffffff5c` .4+<| `DC[2]` <|`7:0` ^| r/w <| 8-bit duty cycle for channel 8
.4+<| `0xfffff00c` .4+<| `DC[2]` <|`7:0` ^| r/w <| 8-bit duty cycle for channel 8
<|`15:8` ^| r/w <| 8-bit duty cycle for channel 9
<|`23:16` ^| r/w <| 8-bit duty cycle for channel 10
<|`31:24` ^| r/w <| 8-bit duty cycle for channel 11

4
docs/datasheet/soc_sdi.adoc
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@ -82,7 +82,7 @@ Furthermore, an active SDI interrupt has to be explicitly cleared again by writi
[options="header",grid="all"]
|=======================
| Address | Name [C] | Bit(s), Name [C] | R/W | Function
.16+<| `0xfffffff0` .16+<| `CTRL` <|`0` `SDI_CTRL_EN` ^| r/w <| SDI module enable
.16+<| `0xfffff700` .16+<| `CTRL` <|`0` `SDI_CTRL_EN` ^| r/w <| SDI module enable
<|`1` `SDI_CTRL_CLR_RX` ^| -/w <| clear RX FIFO when set, bit auto-clears
<|`3:2` _reserved_ ^| r/- <| reserved, read as zero
<|`7:4` `SDI_CTRL_FIFO_MSB : SDI_CTRL_FIFO_LSB` ^| r/- <| FIFO depth; log2(_IO_SDI_FIFO_)
@ -98,5 +98,5 @@ Furthermore, an active SDI interrupt has to be explicitly cleared again by writi
<|`26` `SDI_CTRL_TX_EMPTY` ^| r/- <| TX FIFO empty
<|`27` `SDI_CTRL_TX_FULL` ^| r/- <| TX FIFO full
<|`31:28` _reserved_ ^| r/- <| reserved, read as zero
| `0xfffffff4` | `DATA` |`7:0` | r/w | receive/transmit data (FIFO)
| `0xfffff704` | `DATA` |`7:0` | r/w | receive/transmit data (FIFO)
|=======================

4
docs/datasheet/soc_slink.adoc
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@ -76,7 +76,7 @@ it has to be explicitly cleared again by writing zero to the according <<_mip>>
[options="header",grid="all"]
|=======================
| Address | Name [C] | Bit(s) | R/W | Function
.20+<| `0xffffff08` .20+<| `NEORV32_SLINK.CTRL` <| `0` `SLINK_CTRL_EN` ^| r/w | SLINK global enable
.20+<| `0xffffec00` .20+<| `NEORV32_SLINK.CTRL` <| `0` `SLINK_CTRL_EN` ^| r/w | SLINK global enable
<| `1` `SLINK_CTRL_RX_CLR` ^| -/w | Clear RX FIFO (bit auto-clears)
<| `2` `SLINK_CTRL_TX_CLR` ^| -/w | Clear TX FIFO (bit auto-clears)
<| `7:3` _reserved_ ^| r/- | _reserved_, read as zero
@ -96,5 +96,5 @@ it has to be explicitly cleared again by writing zero to the according <<_mip>>
<| `23:22` _reserved_ ^| r/- | _reserved_, read as zero
<| `27:24` `SLINK_CTRL_RX_FIFO_MSB : SLINK_CTRL_RX_FIFO_LSB` ^| r/- | log2(RX FIFO size)
<| `31:28` `SLINK_CTRL_TX_FIFO_MSB : SLINK_CTRL_TX_FIFO_LSB` ^| r/- | log2(TX FIFO size)
| `0xffffff0c` | `NEORV32_SLINK.DATA` | `31:0` | r/w | RX/TX data
| `0xffffec04` | `NEORV32_SLINK.DATA` | `31:0` | r/w | RX/TX data
|=======================

4
docs/datasheet/soc_spi.adoc
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@ -107,7 +107,7 @@ Furthermore, an active SPI interrupt has to be explicitly cleared again by writi
[options="header",grid="all"]
|=======================
| Address | Name [C] | Bit(s), Name [C] | R/W | Function
.18+<| `0xffffffa8` .18+<| `CTRL` <|`0` `SPI_CTRL_EN` ^| r/w <| SPI module enable
.18+<| `0xfffff800` .18+<| `CTRL` <|`0` `SPI_CTRL_EN` ^| r/w <| SPI module enable
<|`1` `SPI_CTRL_CPHA` ^| r/w <| clock phase
<|`2` `SPI_CTRL_CPOL` ^| r/w <| clock polarity
<|`5:3` `SPI_CTRL_CS_SEL2 : SPI_CTRL_CS_SEL0` ^| r/w <| Direct chip-select 0..7
@ -125,5 +125,5 @@ Furthermore, an active SPI interrupt has to be explicitly cleared again by writi
<|`26:23` `SPI_CTRL_FIFO_MSB : SPI_CTRL_FIFO_LSB` ^| r/- <| FIFO depth; log2(_IO_SPI_FIFO_)
<|`30:27` `reserved_ ^| r/- <| reserved, read as zero
<|`31` `SPI_CTRL_BUSY` ^| r/- <| SPI module busy when set (serial engine operation in progress and TX FIFO not empty yet)
| `0xffffffac` | `DATA` |`7:0` | r/w | receive/transmit data (FIFO)
| `0xfffff804` | `DATA` |`7:0` | r/w | receive/transmit data (FIFO)
|=======================

16
docs/datasheet/soc_sysinfo.adoc
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@ -33,14 +33,14 @@ Any write access to the SYSINFO module will raise a store bus error exception.
[options="header",grid="all"]
|=======================
| Address | Name [C] | Function
| `0xffffffe0` | `CLK` | clock speed in Hz (via top's `CLOCK_FREQUENCY` generic)
| `0xffffffe4` | `CUSTOM_ID | custom user-defined ID (via top's `CUSTOM_ID` generic)
| `0xffffffe8` | `SOC` | specific SoC configuration (see `sysinfo_soc_configuration>>)
| `0xffffffec` | `CACHE` | cache configuration information (see <<_sysinfo_cache_configuration>>)
| `0xfffffff0` | `ISPACE_BASE` | instruction address space base (via package's `ispace_base_c` constant)
| `0xfffffff4` | `IMEM_SIZE` | internal IMEM size in bytes (via top's `MEM_INT_IMEM_SIZE` generic)
| `0xfffffff8` | `DSPACE_BASE` | data address space base (via package's `sdspace_base_c` constant)
| `0xfffffffc` | `DMEM_SIZE` | internal DMEM size in bytes (via top's `MEM_INT_DMEM_SIZE` generic)
| `0xfffffe00` | `CLK` | clock speed in Hz (via top's `CLOCK_FREQUENCY` generic)
| `0xfffffe04` | `CUSTOM_ID | custom user-defined ID (via top's `CUSTOM_ID` generic)
| `0xfffffe08` | `SOC` | specific SoC configuration (see `sysinfo_soc_configuration>>)
| `0xfffffe0c` | `CACHE` | cache configuration information (see <<_sysinfo_cache_configuration>>)
| `0xfffffe10` | `ISPACE_BASE` | instruction address space base (via package's `ispace_base_c` constant)
| `0xfffffe14` | `IMEM_SIZE` | internal IMEM size in bytes (via top's `MEM_INT_IMEM_SIZE` generic)
| `0xfffffe18` | `DSPACE_BASE` | data address space base (via package's `sdspace_base_c` constant)
| `0xfffffe1c` | `DMEM_SIZE` | internal DMEM size in bytes (via top's `MEM_INT_DMEM_SIZE` generic)
|=======================

2
docs/datasheet/soc_trng.adoc
View file

@ -71,7 +71,7 @@ an active TRNG interrupt has to be explicitly cleared again by writing zero to t
[options="header",grid="all"]
|=======================
| Address | Name [C] | Bit(s), Name [C] | R/W | Function
.11+<| `0xffffffb8` .11+<| `CTRL` <|`7:0` `TRNG_CTRL_DATA_MSB : TRNG_CTRL_DATA_MSB` ^| r/- <| 8-bit random data
.11+<| `0xfffffa00` .11+<| `CTRL` <|`7:0` `TRNG_CTRL_DATA_MSB : TRNG_CTRL_DATA_MSB` ^| r/- <| 8-bit random data
<|`15:8` - ^| r/- <| reserved, read as zero
<|`19:16` `TRNG_CTRL_FIFO_MSB : TRNG_CTRL_FIFO_MSB` ^| r/- <| FIFO depth, log2(`IO_TRNG_FIFO`)
<|`25:20` - ^| r/- <| reserved, read as zero

4
docs/datasheet/soc_twi.adoc
View file

@ -125,7 +125,7 @@ explicitly cleared again by writing zero to the according <<_mip>> CSR bit.
[options="header",grid="all"]
|=======================
| Address | Name [C] | Bit(s), Name [C] | R/W | Function
.10+<| `0xffffffb0` .10+<| `CTRL` <|`0` `TWI_CTRL_EN` ^| r/w <| TWI enable, reset if cleared
.10+<| `0xfffff900` .10+<| `CTRL` <|`0` `TWI_CTRL_EN` ^| r/w <| TWI enable, reset if cleared
<|`1` `TWI_CTRL_START` ^| -/w <| generate START condition, auto-clears
<|`2` `TWI_CTRL_STOP` ^| -/w <| generate STOP condition, auto-clears
<|`3` `TWI_CTRL_MACK` ^| r/w <| generate controller-ACK for each transmission ("MACK")
@ -136,5 +136,5 @@ explicitly cleared again by writing zero to the according <<_mip>> CSR bit.
<|`29` `TWI_CTRL_CLAIMED` ^| r/- <| set if the TWI bus is claimed by any controller
<|`30` `TWI_CTRL_ACK` ^| r/- <| ACK received when set, NACK received when cleared
<|`31` `TWI_CTRL_BUSY` ^| r/- <| transfer/START/STOP in progress when set
| `0xffffffb4` | `DATA` |`7:0` | r/w | receive/transmit data
| `0xfffff904` | `DATA` |`7:0` | r/w | receive/transmit data
|=======================

8
docs/datasheet/soc_uart.adoc
View file

@ -122,7 +122,7 @@ Both file are created in the simulation's home folder.
[options="header",grid="all"]
|=======================
| Address | Name [C] | Bit(s), Name [C] | R/W | Function
.19+<| `0xffffffa0` .19+<| `CTRL` <|`0` `UART_CTRL_EN` ^| r/w <| UART enable
.19+<| `0xfffff500` .19+<| `CTRL` <|`0` `UART_CTRL_EN` ^| r/w <| UART enable
<|`1` `UART_CTRL_SIM_MODE` ^| r/w <| enable **simulation mode**
<|`2` `UART_CTRL_HWFC_EN` ^| r/w <| enable RTS/CTS hardware flow-control
<|`5:3` `UART_CTRL_PRSC2 : UART_CTRL_PRSC0` ^| r/w <| Baud rate clock prescaler select
@ -141,7 +141,7 @@ Both file are created in the simulation's home folder.
<|`29:27` - ^| r/- <| _reserved_ read as zero
<|`30` `UART_CTRL_RX_OVER` ^| r/- <| RX FIFO overflow
<|`31` `UART_CTRL_TX_BUSY` ^| r/- <| TX busy or TX FIFO not empty
.5+<| `0xffffffa4` .3+<| `DATA` <|`7:0` `UART_DATA_RTX_MSB : UART_DATA_RTX_LSB` ^| r/w <| receive/transmit data
.5+<| `0xfffff504` .3+<| `DATA` <|`7:0` `UART_DATA_RTX_MSB : UART_DATA_RTX_LSB` ^| r/w <| receive/transmit data
<|`11:8` `UART_DATA_RX_FIFO_SIZE_MSB : UART_DATA_RX_FIFO_SIZE_LSB` ^| r/- <| log2(RX FIFO size)
<|`15:12` `UART_DATA_TX_FIFO_SIZE_MSB : UART_DATA_TX_FIFO_SIZE_LSB` ^| r/- <| log2(RX FIFO size)
<|`31:16` ^| r/- <| _reserved_, read as zero
@ -196,6 +196,6 @@ data words.
[options="header",grid="all"]
|=======================
| Address | Name [C] | Bit(s), Name [C] | R/W | Function
| `0xffffffd0` | `CTRL` | ... | ... | Same as UART0
| `0xffffffd4` | `DATA` | ... | ... | Same as UART0
| `0xfffff600` | `CTRL` | ... | ... | Same as UART0
| `0xfffff604` | `DATA` | ... | ... | Same as UART0
|=======================

2
docs/datasheet/soc_wdt.adoc
View file

@ -84,7 +84,7 @@ the last system reset was caused by the watchdog itself.
[options="header",grid="all"]
|=======================
| Address | Name [C] | Bit(s), Name [C] | R/W | Reset value | Writable if locked | Function
.8+<| `0xffffffbc` .8+<| `CTRL` <|`0` `WDT_CTRL_EN` ^| r/w ^| `0` ^| no <| watchdog enable
.8+<| `0xfffffb00` .8+<| `CTRL` <|`0` `WDT_CTRL_EN` ^| r/w ^| `0` ^| no <| watchdog enable
<|`1 `WDT_CTRL_LOCK` ^| r/w ^| `0` ^| no <| lock configuration when set, clears only on system reset, can only be set if enable bit is set already
<|`2` `WDT_CTRL_DBEN` ^| r/w ^| `0` ^| no <| set to allow WDT to continue operation even when CPU is in debug mode
<|`3` `WDT_CTRL_SEN` ^| r/w ^| `0` ^| no <| set to allow WDT to continue operation even when CPU is in sleep mode

8
docs/datasheet/soc_xirq.adoc
View file

@ -71,8 +71,8 @@ In order to acknowledge an XIRQ interrupt, the interrupt handler has to...
[options="header",grid="all"]
|=======================
| Address | Name [C] | Bit(s) | R/W | Description
| `0xffffff80` | `EIE` | `31:0` | r/w | External interrupt enable register (one bit per channel, LSB-aligned)
| `0xffffff84` | `EIP` | `31:0` | r/w | External interrupt pending register (one bit per channel, LSB-aligned); writing 0 to a bit clears the according pending interrupt
| `0xffffff88` | `ESC` | `4:0` | r/w | Interrupt source ID (0..31) of firing IRQ (prioritized!); writing _any_ value will acknowledge the current XIRQ interrupt
| `0xffffff8c` | - | `31:0` | r/- | _reserved_, read as zero
| `0xfffff300` | `EIE` | `31:0` | r/w | External interrupt enable register (one bit per channel, LSB-aligned)
| `0xfffff304` | `EIP` | `31:0` | r/w | External interrupt pending register (one bit per channel, LSB-aligned); writing 0 to a bit clears the according pending interrupt
| `0xfffff308` | `ESC` | `4:0` | r/w | Interrupt source ID (0..31) of firing IRQ (prioritized!); writing _any_ value will acknowledge the current XIRQ interrupt
| `0xfffff30c` | - | `31:0` | r/- | _reserved_, read as zero
|=======================