some fixes

This commit is contained in:
Pepijn de Vos 2025-03-11 17:54:53 +01:00
parent 2dc9002c4d
commit 1761a0c226
3 changed files with 6 additions and 4 deletions

View file

@ -788,6 +788,7 @@ package neorv32_package is
generic (
-- Processor Clocking --
CLOCK_FREQUENCY : natural := 0;
HART_BASE : natural := 0;
-- Dual-Core Configuration --
DUAL_CORE_EN : boolean := false;
-- Boot Configuration --

View file

@ -22,6 +22,7 @@ entity neorv32_top is
generic (
-- Processor Clocking --
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
HART_BASE : natural := 0; -- offset in HART_IDs
-- Dual-Core Configuration --
DUAL_CORE_EN : boolean := false; -- enable dual-core homogeneous SMP
@ -488,7 +489,7 @@ begin
neorv32_cpu_inst: entity neorv32.neorv32_cpu
generic map (
-- General --
HART_ID => i,
HART_ID => i+HART_BASE,
BOOT_ADDR => cpu_boot_addr_c,
DEBUG_PARK_ADDR => dm_park_entry_c,
DEBUG_EXC_ADDR => dm_exc_entry_c,

View file

@ -102,8 +102,8 @@ architecture neorv32_litex_core_complex_rtl of neorv32_litex_core_complex is
pmp_num => ( 0, 0, 0, 8, 0 ), -- number of PMP regions (0..16)
hpm_num => ( 0, 0, 0, 8, 0 ), -- number of HPM counters (0..29)
xcache_en => ( false, false, true, true, false ), -- external bus cache enabled
xcache_nb => ( 0, 0, 32, 64, 0 ), -- number of cache blocks (lines), power of two
xcache_bs => ( 0, 0, 32, 32, 0 ), -- size of cache clock (lines) in bytes, power of two
xcache_nb => ( 32, 32, 32, 64, 32 ), -- number of cache blocks (lines), power of two
xcache_bs => ( 32, 32, 32, 32, 32 ), -- size of cache clock (lines) in bytes, power of two
clint => ( false, true, true, true, true ) -- RISC-V core local interruptor
);
@ -118,7 +118,7 @@ begin
generic map (
-- General --
CLOCK_FREQUENCY => 0, -- clock frequency of clk_i in Hz [not required by the core complex]
HART_ID => HART_ID,
HART_BASE => HART_ID,
-- On-Chip Debugger (OCD) --
OCD_EN => DEBUG, -- implement on-chip debugger
-- RISC-V CPU Extensions --