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some fixes
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parent
2dc9002c4d
commit
1761a0c226
3 changed files with 6 additions and 4 deletions
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@ -788,6 +788,7 @@ package neorv32_package is
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generic (
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-- Processor Clocking --
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CLOCK_FREQUENCY : natural := 0;
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HART_BASE : natural := 0;
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-- Dual-Core Configuration --
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DUAL_CORE_EN : boolean := false;
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-- Boot Configuration --
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@ -22,6 +22,7 @@ entity neorv32_top is
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generic (
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-- Processor Clocking --
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CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
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HART_BASE : natural := 0; -- offset in HART_IDs
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-- Dual-Core Configuration --
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DUAL_CORE_EN : boolean := false; -- enable dual-core homogeneous SMP
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@ -488,7 +489,7 @@ begin
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neorv32_cpu_inst: entity neorv32.neorv32_cpu
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generic map (
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-- General --
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HART_ID => i,
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HART_ID => i+HART_BASE,
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BOOT_ADDR => cpu_boot_addr_c,
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DEBUG_PARK_ADDR => dm_park_entry_c,
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DEBUG_EXC_ADDR => dm_exc_entry_c,
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@ -102,8 +102,8 @@ architecture neorv32_litex_core_complex_rtl of neorv32_litex_core_complex is
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pmp_num => ( 0, 0, 0, 8, 0 ), -- number of PMP regions (0..16)
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hpm_num => ( 0, 0, 0, 8, 0 ), -- number of HPM counters (0..29)
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xcache_en => ( false, false, true, true, false ), -- external bus cache enabled
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xcache_nb => ( 0, 0, 32, 64, 0 ), -- number of cache blocks (lines), power of two
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xcache_bs => ( 0, 0, 32, 32, 0 ), -- size of cache clock (lines) in bytes, power of two
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xcache_nb => ( 32, 32, 32, 64, 32 ), -- number of cache blocks (lines), power of two
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xcache_bs => ( 32, 32, 32, 32, 32 ), -- size of cache clock (lines) in bytes, power of two
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clint => ( false, true, true, true, true ) -- RISC-V core local interruptor
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);
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@ -118,7 +118,7 @@ begin
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generic map (
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-- General --
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CLOCK_FREQUENCY => 0, -- clock frequency of clk_i in Hz [not required by the core complex]
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HART_ID => HART_ID,
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HART_BASE => HART_ID,
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-- On-Chip Debugger (OCD) --
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OCD_EN => DEBUG, -- implement on-chip debugger
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-- RISC-V CPU Extensions --
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