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[sw/lib] add helper for register spilling

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stnolting 2023-12-11 21:42:54 +01:00
parent d6167b90d6
commit 196ba488ba
1 changed files with 111 additions and 4 deletions
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115
sw/lib/include/neorv32_cpu.h
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@ -64,7 +64,114 @@ void neorv32_cpu_goto_user_mode(void);
// #################################################################################################
// Load/store
// Context save/restore helpers
// #################################################################################################
/**********************************************************************//**
* Save all integer registers to the stack.
*
* @note This inlined function automatically constrains the number
* of registers when compiling for rv32e (only 16 registers).
**************************************************************************/
inline void __attribute__ ((always_inline)) neorv32_context_save(void) {
// do not backup x0 and sp
asm volatile (
#ifndef __riscv_32e
"addi sp, sp, -30*4 \n"
#else
"addi sp, sp, -14*4 \n"
#endif
"sw x1, 0*4(sp) \n"
"sw x3, 1*4(sp) \n"
"sw x4, 2*4(sp) \n"
"sw x5, 3*4(sp) \n"
"sw x6, 4*4(sp) \n"
"sw x7, 5*4(sp) \n"
"sw x8, 6*4(sp) \n"
"sw x9, 7*4(sp) \n"
"sw x10, 8*4(sp) \n"
"sw x11, 9*4(sp) \n"
"sw x12, 10*4(sp) \n"
"sw x13, 11*4(sp) \n"
"sw x14, 12*4(sp) \n"
"sw x15, 13*4(sp) \n"
#ifndef __riscv_32e
"sw x16, 14*4(sp) \n"
"sw x17, 15*4(sp) \n"
"sw x18, 16*4(sp) \n"
"sw x19, 17*4(sp) \n"
"sw x20, 18*4(sp) \n"
"sw x21, 19*4(sp) \n"
"sw x22, 20*4(sp) \n"
"sw x23, 21*4(sp) \n"
"sw x24, 22*4(sp) \n"
"sw x25, 23*4(sp) \n"
"sw x26, 24*4(sp) \n"
"sw x27, 25*4(sp) \n"
"sw x28, 26*4(sp) \n"
"sw x29, 27*4(sp) \n"
"sw x30, 28*4(sp) \n"
"sw x31, 29*4(sp) \n"
#endif
);
}
/**********************************************************************//**
* Restore all integer registers from the stack.
*
* @note This inlined function automatically constrains the number
* of registers when compiling for rv32e (only 16 registers).
**************************************************************************/
inline void __attribute__ ((always_inline)) neorv32_context_restore(void) {
// do not restore x0 and sp
asm volatile (
"lw x1, 0*4(sp) \n"
"lw x3, 1*4(sp) \n"
"lw x4, 2*4(sp) \n"
"lw x5, 3*4(sp) \n"
"lw x6, 4*4(sp) \n"
"lw x7, 5*4(sp) \n"
"lw x8, 6*4(sp) \n"
"lw x9, 7*4(sp) \n"
"lw x10, 8*4(sp) \n"
"lw x11, 9*4(sp) \n"
"lw x12, 10*4(sp) \n"
"lw x13, 11*4(sp) \n"
"lw x14, 12*4(sp) \n"
"lw x15, 13*4(sp) \n"
#ifndef __riscv_32e
"lw x16, 14*4(sp) \n"
"lw x17, 15*4(sp) \n"
"lw x18, 16*4(sp) \n"
"lw x19, 17*4(sp) \n"
"lw x20, 18*4(sp) \n"
"lw x21, 19*4(sp) \n"
"lw x22, 20*4(sp) \n"
"lw x23, 21*4(sp) \n"
"lw x24, 22*4(sp) \n"
"lw x25, 23*4(sp) \n"
"lw x26, 24*4(sp) \n"
"lw x27, 25*4(sp) \n"
"lw x28, 26*4(sp) \n"
"lw x29, 27*4(sp) \n"
"lw x30, 28*4(sp) \n"
"lw x31, 29*4(sp) \n"
#endif
#ifndef __riscv_32e
"addi sp, sp, +30*4 \n"
#else
"addi sp, sp, +14*4 \n"
#endif
"ret \n"
);
}
// #################################################################################################
// Load/store helpers
// #################################################################################################
@ -209,7 +316,7 @@ inline int8_t __attribute__ ((always_inline)) neorv32_cpu_load_signed_byte(uint3
// #################################################################################################
// Atomic memory access / load-reservate/store-conditional
// Atomic memory access / load-reservate/store-conditional helpers
// #################################################################################################
@ -282,7 +389,7 @@ inline void __attribute__ ((always_inline)) neorv32_cpu_invalidate_reservations(
// #################################################################################################
// CSR access
// CSR access helpers
// #################################################################################################
@ -345,7 +452,7 @@ inline void __attribute__ ((always_inline)) neorv32_cpu_csr_clr(const int csr_id
// #################################################################################################
// Misc
// Misc helpers
// #################################################################################################