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🚀 preparing release 1.9.0

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stnolting 2023-10-13 16:43:11 +02:00
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commit 1d689324db
4 changed files with 4 additions and 3 deletions
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1
CHANGELOG.md
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@ -32,6 +32,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
| Date (*dd.mm.yyyy*) | Version | Comment |
|:-------------------:|:-------:|:--------|
| 13.10.2023 | [**:rocket:1.9.0**](https://github.com/stnolting/neorv32/releases/tag/v1.9.0) | **New release** |
| 13.10.2023 | 1.8.9.9 | minor hardware edits and optimizations; [#703](https://github.com/stnolting/neorv32/pull/703) |
| 07.10.2023 | 1.8.9.8 | add "transfer done" flag to DMA; [#699](https://github.com/stnolting/neorv32/pull/699) |
| 04.10.2023 | 1.8.9.7 | :warning: rework internal bus protocol; [#697](https://github.com/stnolting/neorv32/pull/697) |

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docs/attrs.adoc
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@ -1,7 +1,7 @@
:author: by stnolting
:keywords: neorv32, risc-v, riscv, rv32, fpga, soft-core, vhdl, microcontroller, cpu, soc, processor, gcc, openocd, gdb
:description: A size-optimized, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
:revnumber: v1.8.9
:revnumber: v1.9.0
:doctype: book
:sectnums:
:stem:

2
rtl/core/neorv32_package.vhd
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@ -59,7 +59,7 @@ package neorv32_package is
-- Architecture Constants -----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01080909"; -- hardware version
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01090000"; -- hardware version
constant archid_c : natural := 19; -- official RISC-V architecture ID
constant XLEN : natural := 32; -- native data path width, do not change!

2
sw/svd/neorv32.svd
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@ -4,7 +4,7 @@
<vendor>stnolting</vendor>
<name>neorv32</name>
<series>RISC-V</series>
<version>1.8.9</version>
<version>1.9.0</version>
<description>The NEORV32 RISC-V Processor</description>
<!-- CPU core -->