github-mirrors/neorv32
1
0
Fork 0
mirror of https://github.com/stnolting/neorv32.git synced 2025-04-24 06:07:52 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

⚠️ remove top's HART_ID generic

Browse source 
MHARTID is hardwired to zero
This commit is contained in:
stnolting 2024-12-27 06:41:42 +01:00
parent b1b96c4f25
commit 22384e1a80
9 changed files with 4 additions and 14 deletions
Download patch file Download diff file Expand all files Collapse all files

2
CHANGELOG.md
View file

@ -29,7 +29,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
| Date | Version | Comment | Ticket |
|:----:|:-------:|:--------|:------:|
| 27.12.2024 | 1.10.8.1 | :warning: replace MTIME by CLINT | [#1130](https://github.com/stnolting/neorv32/pull/1130) |
| 27.12.2024 | 1.10.8.1 | :warning: replace MTIME by CLINT; :warning: remove `HART_ID` generic | [#1130](https://github.com/stnolting/neorv32/pull/1130) |
| 26.12.2024 | [**:rocket:1.10.8**](https://github.com/stnolting/neorv32/releases/tag/v1.10.8) | **New release** | |
| 23.12.2024 | 1.10.7.9 | :warning: rework IO/peripheral address space; :sparkles: increase device size from 256 bytes to 64kB | [#1126](https://github.com/stnolting/neorv32/pull/1126) |
| 22.12.2024 | 1.10.7.8 | :warning: rename CPU tuning options / generics | [#1125](https://github.com/stnolting/neorv32/pull/1125) |

3
docs/datasheet/cpu_csr.adoc
View file

@ -904,8 +904,7 @@ NEORV32 as BCD-coded number (example: `mimpid = 0x01020312` → 01.02.03.12 →
| Address | `0xf14`
| Reset value | `DEFINED`
| ISA | `Zicsr`
| Description | The `mhartid` CSR is read-only and provides the core's hart ID,
which is assigned via the `HW_THREAD_ID` top generic (<<_processor_top_entity_generics>>).
| Description | The `mhartid` CSR is read-only and provides the core's hart ID which is hardwired to zero.
|=======================

1
docs/datasheet/soc.adoc
View file

@ -211,7 +211,6 @@ The generic type "`suv(x:y)`" is an abbreviation for "`std_ulogic_vector(x downt
4+^| **<<_processor_clocking>>**
| `CLOCK_FREQUENCY` | natural | 0 | The clock frequency of the processor's `clk_i` input port in Hertz (Hz).
4+^| **Core Identification**
| `HART_ID` | suv(31:0) | x"00000000" | The hart thread ID of the CPU (passed to <<_mhartid>> CSR).
| `JEDEC_ID` | suv(10:0) | "00000000000" | JEDEC ID; continuation codes plus vendor ID (passed to <<_mvendorid>> CSR and to the <<_debug_transport_module_dtm>>).
4+^| **<<_boot_configuration>>**
| `BOOT_MODE_SELECT` | natural | 0 | Boot mode select; see <<_boot_configuration>>.

1
rtl/core/neorv32_package.vhd
View file

@ -717,7 +717,6 @@ package neorv32_package is
-- Processor Clocking --
CLOCK_FREQUENCY : natural := 0;
-- Identification --
HART_ID : std_ulogic_vector(31 downto 0) := x"00000000";
JEDEC_ID : std_ulogic_vector(10 downto 0) := "00000000000";
-- Boot Configuration --
BOOT_MODE_SELECT : natural range 0 to 2 := 0;

3
rtl/core/neorv32_top.vhd
View file

@ -25,7 +25,6 @@ entity neorv32_top is
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
-- Core Identification --
HART_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- hardware thread ID
JEDEC_ID : std_ulogic_vector(10 downto 0) := "00000000000"; -- JEDEC ID: continuation codes + vendor ID
-- Boot Configuration --
@ -468,7 +467,7 @@ begin
neorv32_cpu_inst: entity neorv32.neorv32_cpu
generic map (
-- General --
HART_ID => HART_ID,
HART_ID => 0,
VENDOR_ID => vendorid_c,
BOOT_ADDR => cpu_boot_addr_c,
DEBUG_PARK_ADDR => dm_park_entry_c,

4
rtl/system_integration/neorv32_litex_core_complex.vhd
View file

@ -68,8 +68,7 @@ end neorv32_litex_core_complex;
architecture neorv32_litex_core_complex_rtl of neorv32_litex_core_complex is
-- identifiers --
constant hart_id_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- hardware thread ID ("core ID")
-- core identification --
constant jedec_id_c : std_ulogic_vector(10 downto 0) := "00000000000"; -- vendor's JEDEC manufacturer ID
-- configuration helpers --
@ -119,7 +118,6 @@ begin
generic map (
-- General --
CLOCK_FREQUENCY => 0, -- clock frequency of clk_i in Hz [not required by the core complex]
HART_ID => hart_id_c, -- hardware thread ID
JEDEC_ID => jedec_id_c, -- vendor's JEDEC ID
-- On-Chip Debugger (OCD) --
OCD_EN => DEBUG, -- implement on-chip debugger

1
rtl/system_integration/neorv32_vivado_ip.tcl
View file

@ -172,7 +172,6 @@ proc setup_ip_gui {} {
set group [add_group $page {Core Identification}]
add_params $group {
{ HART_ID {HART ID} {The hart thread ID of the CPU (passed to mhartid CSR)} }
{ JEDEC_ID {JEDEC ID} {For JTAG tap identification and mvendorid CSR} }
}

2
rtl/system_integration/neorv32_vivado_ip.vhd
View file

@ -28,7 +28,6 @@ entity neorv32_vivado_ip is
-- Clocking --
CLOCK_FREQUENCY : natural := 100_000_000;
-- Identification --
HART_ID : std_logic_vector(31 downto 0) := x"00000000";
JEDEC_ID : std_logic_vector(10 downto 0) := "00000000000";
-- Boot Configuration --
BOOT_MODE_SELECT : natural range 0 to 2 := 0;
@ -355,7 +354,6 @@ begin
-- Clocking --
CLOCK_FREQUENCY => CLOCK_FREQUENCY,
-- Identification --
HART_ID => std_ulogic_vector(HART_ID),
JEDEC_ID => std_ulogic_vector(JEDEC_ID),
-- Boot Configuration --
BOOT_MODE_SELECT => BOOT_MODE_SELECT,

1
sim/neorv32_tb.vhd
View file

@ -111,7 +111,6 @@ begin
-- Clocking --
CLOCK_FREQUENCY => CLOCK_FREQUENCY,
-- Identification --
HART_ID => x"00000000",
JEDEC_ID => "00000000000",
-- Boot Configuration --
BOOT_MODE_SELECT => BOOT_MODE_SELECT,