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emb4fun 2023-03-10 20:03:35 +01:00
parent e8b37bdd89
commit 236614dc53
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18 changed files with 739 additions and 639 deletions
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sw/lib/include/neorv32.h
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@ -670,651 +670,36 @@ enum NEORV32_CLOCK_PRSC_enum {
/**@}*/
// ############################################################################################################################
// On-Chip Debugger (should NOT be used by application software at all!)
// ############################################################################################################################
/**@{*/
/** on-chip debugger - debug module prototype */
typedef volatile struct __attribute__((packed,aligned(4))) {
const uint32_t CODE[16]; /**< offset 0: park loop code ROM (r/-) */
const uint32_t PBUF[4]; /**< offset 64: program buffer (r/-) */
const uint32_t reserved1[12]; /**< reserved */
uint32_t DATA; /**< offset 128: data exchange register (r/w) */
const uint32_t reserved2[15]; /**< reserved */
uint32_t SREG; /**< offset 192: control and status register (r/w) */
const uint32_t reserved3[15]; /**< reserved */
} neorv32_dm_t;
/** on-chip debugger debug module base address */
#define NEORV32_DM_BASE (0XFFFFF800U)
/** on-chip debugger debug module hardware access (#neorv32_dm_t) */
#define NEORV32_DM ((neorv32_dm_t*) (NEORV32_DM_BASE))
/**@}*/
// ############################################################################################################################
// #################################################################################################
// Peripheral/IO Devices - IO Address Space
// ############################################################################################################################
// #################################################################################################
/**********************************************************************//**
* @name IO Device: Custom Functions Subsystem (CFS)
* @name Peripheral/IO Devices - IO Address Space - base addresses
**************************************************************************/
/**@{*/
/** CFS module prototype */
typedef volatile struct __attribute__((packed,aligned(4))) {
uint32_t REG[64]; /**< offset 4*0..4*63: CFS register 0..63, user-defined */
} neorv32_cfs_t;
/** CFS base address */
#define NEORV32_CFS_BASE (0xFFFFFE00U)
#define NEORV32_SYSINFO_BASE (0xFFFFFFE0U) /* System Configuration Information Memory (SYSINFO) */
#define NEORV32_NEOLED_BASE (0xFFFFFFD8U) /* Smart LED Hardware Interface (NEOLED) */
#define NEORV32_UART1_BASE (0xFFFFFFD0U) /* Secondary Universal Asynchronous Receiver and Transmitter (UART1) */
#define NEORV32_GPIO_BASE (0xFFFFFFC0U) /* General Purpose Input/Output Port Unit (GPIO) */
#define NEORV32_WDT_BASE (0xFFFFFFBCU) /* Watchdog Timer (WDT) */
#define NEORV32_TRNG_BASE (0xFFFFFFB8U) /* True Random Number Generator (TRNG) */
#define NEORV32_TWI_BASE (0xFFFFFFB0U) /* Two-Wire Interface Controller (TWI) */
#define NEORV32_SPI_BASE (0xFFFFFFA8U) /* Serial Peripheral Interface Controller (SPI) */
#define NEORV32_UART0_BASE (0xFFFFFFA0U) /* Primary Universal Asynchronous Receiver and Transmitter (UART0) */
#define NEORV32_MTIME_BASE (0xFFFFFF90U) /* Machine System Timer (MTIME) */
#define NEORV32_XIRQ_BASE (0xFFFFFF80U) /* External Interrupt Controller (XIRQ) */
#define NEORV32_BUSKEEPER_BASE (0xFFFFFF78U) /* Bus Monitor (BUSKEEPER) */
#define NEORV32_ONEWIRE_BASE (0xFFFFFF70U) /* 1-Wire Interface Controller (ONEWIRE) */
#define NEORV32_GPTMR_BASE (0xFFFFFF60U) /* General Purpose Timer (GPTMR) */
#define NEORV32_PWM_BASE (0xFFFFFF50U) /* Pulse Width Modulation Controller (PWM) */
#define NEORV32_XIP_BASE (0xFFFFFF40U) /* Execute In Place Module (XIP) */
#define NEORV32_SDI_BASE (0xFFFFFF00U) /* Serial Data Interface (SDI) */
#define NEORV32_CFS_BASE (0xFFFFFE00U) /* Custom Functions Subsystem (CFS) */
#define NEORV32_DM_BASE (0xFFFFF800U) /* On-Chip Debugger */
/** CFS module hardware access (#neorv32_cfs_t) */
#define NEORV32_CFS ((neorv32_cfs_t*) (NEORV32_CFS_BASE))
/**@}*/
/**********************************************************************//**
* @name IO Device: Serial Data Interface (SDI)
**************************************************************************/
/**@{*/
/** SDI module prototype */
typedef volatile struct __attribute__((packed,aligned(4))) {
uint32_t CTRL; /**< offset 0: control register (#NEORV32_SDI_CTRL_enum) */
uint32_t DATA; /**< offset 4: data register */
} neorv32_sdi_t;
/** SDI module base address */
#define NEORV32_SDI_BASE (0xFFFFFF00U)
/** SDI module hardware access (#neorv32_sdi_t) */
#define NEORV32_SDI ((neorv32_sdi_t*) (NEORV32_SDI_BASE))
/** SDI control register bits */
enum NEORV32_SDI_CTRL_enum {
SDI_CTRL_EN = 0, /**< SDI control register(00) (r/w): SID module enable */
SDI_CTRL_CLR_RX = 1, /**< SDI control register(01) (-/w): Clear RX FIFO when set, auto-clear */
SDI_CTRL_FIFO_LSB = 4, /**< SDI control register(04) (r/-): log2 of SDI FIFO size, LSB */
SDI_CTRL_FIFO_MSB = 7, /**< SDI control register(07) (r/-): log2 of SDI FIFO size, MSB */
SDI_CTRL_IRQ_RX_AVAIL = 15, /**< SDI control register(15) (r/w): IRQ when RX FIFO not empty */
SDI_CTRL_IRQ_RX_HALF = 16, /**< SDI control register(16) (r/w): IRQ when RX FIFO at least half full */
SDI_CTRL_IRQ_RX_FULL = 17, /**< SDI control register(17) (r/w): IRQ when RX FIFO full */
SDI_CTRL_IRQ_TX_EMPTY = 18, /**< SDI control register(18) (r/w): IRQ when TX FIFO empty */
SDI_CTRL_RX_AVAIL = 23, /**< SDI control register(23) (r/-): RX FIFO not empty */
SDI_CTRL_RX_HALF = 24, /**< SDI control register(24) (r/-): RX FIFO at least half full */
SDI_CTRL_RX_FULL = 25, /**< SDI control register(25) (r/-): RX FIFO full */
SDI_CTRL_TX_EMPTY = 26, /**< SDI control register(26) (r/-): TX FIFO empty */
SDI_CTRL_TX_FULL = 27 /**< SDI control register(27) (r/-): TX FIFO full */
};
/**@}*/
/**********************************************************************//**
* @name IO Device: Execute In Place Module (XIP)
**************************************************************************/
/**@{*/
/** XIP module prototype */
typedef volatile struct __attribute__((packed,aligned(4))) {
uint32_t CTRL; /**< offset 0: control register (#NEORV32_XIP_CTRL_enum) */
const uint32_t reserved; /**< offset 4: reserved */
uint32_t DATA_LO; /**< offset 8: SPI data register low */
uint32_t DATA_HI; /**< offset 12: SPI data register high */
} neorv32_xip_t;
/** XIP module base address */
#define NEORV32_XIP_BASE (0xFFFFFF40U)
/** XIP module hardware access (#neorv32_xip_t) */
#define NEORV32_XIP ((neorv32_xip_t*) (NEORV32_XIP_BASE))
/** XIP control/data register bits */
enum NEORV32_XIP_CTRL_enum {
XIP_CTRL_EN = 0, /**< XIP control register( 0) (r/w): XIP module enable */
XIP_CTRL_PRSC0 = 1, /**< XIP control register( 1) (r/w): Clock prescaler select bit 0 */
XIP_CTRL_PRSC1 = 2, /**< XIP control register( 2) (r/w): Clock prescaler select bit 1 */
XIP_CTRL_PRSC2 = 3, /**< XIP control register( 3) (r/w): Clock prescaler select bit 2 */
XIP_CTRL_CPOL = 4, /**< XIP control register( 4) (r/w): SPI (idle) clock polarity */
XIP_CTRL_CPHA = 5, /**< XIP control register( 5) (r/w): SPI clock phase */
XIP_CTRL_SPI_NBYTES_LSB = 6, /**< XIP control register( 6) (r/w): Number of bytes in SPI transmission, LSB */
XIP_CTRL_SPI_NBYTES_MSB = 9, /**< XIP control register( 9) (r/w): Number of bytes in SPI transmission, MSB */
XIP_CTRL_XIP_EN = 10, /**< XIP control register(10) (r/w): XIP access enable */
XIP_CTRL_XIP_ABYTES_LSB = 11, /**< XIP control register(11) (r/w): Number XIP address bytes (minus 1), LSB */
XIP_CTRL_XIP_ABYTES_MSB = 12, /**< XIP control register(12) (r/w): Number XIP address bytes (minus 1), MSB */
XIP_CTRL_RD_CMD_LSB = 13, /**< XIP control register(13) (r/w): SPI flash read command, LSB */
XIP_CTRL_RD_CMD_MSB = 20, /**< XIP control register(20) (r/w): SPI flash read command, MSB */
XIP_CTRL_PAGE_LSB = 21, /**< XIP control register(21) (r/w): XIP memory page, LSB */
XIP_CTRL_PAGE_MSB = 24, /**< XIP control register(24) (r/w): XIP memory page, MSB */
XIP_CTRL_SPI_CSEN = 25, /**< XIP control register(25) (r/w): SPI chip-select enable */
XIP_CTRL_HIGHSPEED = 26, /**< XIP control register(26) (r/w): SPI high-speed mode enable (ignoring XIP_CTRL_PRSC) */
XIP_CTRL_BURST_EN = 27, /**< XIP control register(27) (r/w): Enable XIP burst mode */
XIP_CTRL_PHY_BUSY = 30, /**< XIP control register(20) (r/-): SPI PHY is busy */
XIP_CTRL_XIP_BUSY = 31 /**< XIP control register(31) (r/-): XIP access in progress */
};
/**@}*/
/**********************************************************************//**
* @name IO Device: Pulse Width Modulation Controller (PWM)
**************************************************************************/
/**@{*/
/** PWM module prototype */
typedef volatile struct __attribute__((packed,aligned(4))) {
uint32_t CTRL; /**< offset 0: control register (#NEORV32_PWM_CTRL_enum) */
uint32_t DC[3]; /**< offset 4..12: duty cycle register 0..2 */
} neorv32_pwm_t;
/** PWM module base address */
#define NEORV32_PWM_BASE (0xFFFFFF50U)
/** PWM module hardware access (#neorv32_pwm_t) */
#define NEORV32_PWM ((neorv32_pwm_t*) (NEORV32_PWM_BASE))
/** PWM control register bits */
enum NEORV32_PWM_CTRL_enum {
PWM_CTRL_EN = 0, /**< PWM control register(0) (r/w): PWM controller enable */
PWM_CTRL_PRSC0 = 1, /**< PWM control register(1) (r/w): Clock prescaler select bit 0 */
PWM_CTRL_PRSC1 = 2, /**< PWM control register(2) (r/w): Clock prescaler select bit 1 */
PWM_CTRL_PRSC2 = 3 /**< PWM control register(3) (r/w): Clock prescaler select bit 2 */
};
/**@}*/
/**********************************************************************//**
* @name IO Device: General Purpose Timer (GPTMR)
**************************************************************************/
/**@{*/
/** GPTMR module prototype */
typedef volatile struct __attribute__((packed,aligned(4))) {
uint32_t CTRL; /**< offset 0: control register (#NEORV32_GPTMR_CTRL_enum) */
uint32_t THRES; /**< offset 4: threshold register */
uint32_t COUNT; /**< offset 8: counter register */
const uint32_t reserved; /**< offset 12: reserved */
} neorv32_gptmr_t;
/** GPTMR module base address */
#define NEORV32_GPTMR_BASE (0xFFFFFF60U)
/** GPTMR module hardware access (#neorv32_gptmr_t) */
#define NEORV32_GPTMR ((neorv32_gptmr_t*) (NEORV32_GPTMR_BASE))
/** GPTMR control/data register bits */
enum NEORV32_GPTMR_CTRL_enum {
GPTMR_CTRL_EN = 0, /**< GPTIMR control register(0) (r/w): Timer unit enable */
GPTMR_CTRL_PRSC0 = 1, /**< GPTIMR control register(1) (r/w): Clock prescaler select bit 0 */
GPTMR_CTRL_PRSC1 = 2, /**< GPTIMR control register(2) (r/w): Clock prescaler select bit 1 */
GPTMR_CTRL_PRSC2 = 3, /**< GPTIMR control register(3) (r/w): Clock prescaler select bit 2 */
GPTMR_CTRL_MODE = 4 /**< GPTIMR control register(4) (r/w): Timer mode: 0=single-shot mode, 1=continuous mode */
};
/**@}*/
/**********************************************************************//**
* @name IO Device: 1-Wire Interface Controller (ONEWIRE)
**************************************************************************/
/**@{*/
/** ONEWIRE module prototype */
typedef volatile struct __attribute__((packed,aligned(4))) {
uint32_t CTRL; /**< offset 0: control register (#NEORV32_ONEWIRE_CTRL_enum) */
uint32_t DATA; /**< offset 4: transmission data register (#NEORV32_ONEWIRE_DATA_enum) */
} neorv32_onewire_t;
/** ONEWIRE module base address */
#define NEORV32_ONEWIRE_BASE (0xFFFFFF70U)
/** ONEWIRE module hardware access (#neorv32_onewire_t) */
#define NEORV32_ONEWIRE ((neorv32_onewire_t*) (NEORV32_ONEWIRE_BASE))
/** ONEWIRE control register bits */
enum NEORV32_ONEWIRE_CTRL_enum {
ONEWIRE_CTRL_EN = 0, /**< ONEWIRE control register(0) (r/w): ONEWIRE controller enable */
ONEWIRE_CTRL_PRSC0 = 1, /**< ONEWIRE control register(1) (r/w): Clock prescaler select bit 0 */
ONEWIRE_CTRL_PRSC1 = 2, /**< ONEWIRE control register(2) (r/w): Clock prescaler select bit 1 */
ONEWIRE_CTRL_CLKDIV0 = 3, /**< ONEWIRE control register(3) (r/w): Clock divider bit 0 */
ONEWIRE_CTRL_CLKDIV1 = 4, /**< ONEWIRE control register(4) (r/w): Clock divider bit 1 */
ONEWIRE_CTRL_CLKDIV2 = 5, /**< ONEWIRE control register(5) (r/w): Clock divider bit 2 */
ONEWIRE_CTRL_CLKDIV3 = 6, /**< ONEWIRE control register(6) (r/w): Clock divider bit 3 */
ONEWIRE_CTRL_CLKDIV4 = 7, /**< ONEWIRE control register(7) (r/w): Clock divider bit 4 */
ONEWIRE_CTRL_CLKDIV5 = 8, /**< ONEWIRE control register(8) (r/w): Clock divider bit 5 */
ONEWIRE_CTRL_CLKDIV6 = 9, /**< ONEWIRE control register(9) (r/w): Clock divider bit 6 */
ONEWIRE_CTRL_CLKDIV7 = 10, /**< ONEWIRE control register(10) (r/w): Clock divider bit 7 */
ONEWIRE_CTRL_TRIG_RST = 11, /**< ONEWIRE control register(11) (-/w): Trigger reset pulse, auto-clears */
ONEWIRE_CTRL_TRIG_BIT = 12, /**< ONEWIRE control register(12) (-/w): Trigger single-bit transmission, auto-clears */
ONEWIRE_CTRL_TRIG_BYTE = 13, /**< ONEWIRE control register(13) (-/w): Trigger full-byte transmission, auto-clears */
ONEWIRE_CTRL_SENSE = 29, /**< ONEWIRE control register(29) (r/-): Current state of the bus line */
ONEWIRE_CTRL_PRESENCE = 30, /**< ONEWIRE control register(30) (r/-): Bus presence detected */
ONEWIRE_CTRL_BUSY = 31, /**< ONEWIRE control register(31) (r/-): Operation in progress when set */
};
/** ONEWIRE receive/transmit data register bits */
enum NEORV32_ONEWIRE_DATA_enum {
ONEWIRE_DATA_LSB = 0, /**< ONEWIRE data register(0) (r/w): Receive/transmit data (8-bit) LSB */
ONEWIRE_DATA_MSB = 7 /**< ONEWIRE data register(7) (r/w): Receive/transmit data (8-bit) MSB */
};
/**@}*/
/**********************************************************************//**
* @name IO Device: Bus Monitor (BUSKEEPER)
**************************************************************************/
/**@{*/
/** BUSKEEPER module prototype */
typedef volatile struct __attribute__((packed,aligned(4))) {
uint32_t CTRL; /**< offset 0: control register (#NEORV32_BUSKEEPER_CTRL_enum) */
const uint32_t reserved ; /**< offset 4: reserved */
} neorv32_buskeeper_t;
/** BUSKEEPER module base address */
#define NEORV32_BUSKEEPER_BASE (0xFFFFFF78U)
/** BUSKEEPER module hardware access (#neorv32_buskeeper_t) */
#define NEORV32_BUSKEEPER ((neorv32_buskeeper_t*) (NEORV32_BUSKEEPER_BASE))
/** BUSKEEPER control/data register bits */
enum NEORV32_BUSKEEPER_CTRL_enum {
BUSKEEPER_ERR_TYPE = 0, /**< BUSKEEPER control register( 0) (r/-): Bus error type: 0=device error, 1=access timeout */
BUSKEEPER_ERR_FLAG = 31 /**< BUSKEEPER control register(31) (r/-): Sticky error flag, clears after read or write access */
};
/**@}*/
/**********************************************************************//**
* @name IO Device: External Interrupt Controller (XIRQ)
**************************************************************************/
/**@{*/
/** XIRQ module prototype */
typedef volatile struct __attribute__((packed,aligned(4))) {
uint32_t IER; /**< offset 0: IRQ input enable register */
uint32_t IPR; /**< offset 4: pending IRQ register /ack/clear */
uint32_t SCR; /**< offset 8: interrupt source register */
const uint32_t reserved; /**< offset 12: reserved */
} neorv32_xirq_t;
/** XIRQ module base address */
#define NEORV32_XIRQ_BASE (0xFFFFFF80U)
/** XIRQ module hardware access (#neorv32_xirq_t) */
#define NEORV32_XIRQ ((neorv32_xirq_t*) (NEORV32_XIRQ_BASE))
/**@}*/
/**********************************************************************//**
* @name IO Device: Machine System Timer (MTIME)
**************************************************************************/
/**@{*/
/** MTIME module prototype */
typedef volatile struct __attribute__((packed,aligned(4))) {
uint32_t TIME_LO; /**< offset 0: time register low word */
uint32_t TIME_HI; /**< offset 4: time register high word */
uint32_t TIMECMP_LO; /**< offset 8: compare register low word */
uint32_t TIMECMP_HI; /**< offset 12: compare register high word */
} neorv32_mtime_t;
/** MTIME module base address */
#define NEORV32_MTIME_BASE (0xFFFFFF90U)
/** MTIME module hardware access (#neorv32_mtime_t) */
#define NEORV32_MTIME ((neorv32_mtime_t*) (NEORV32_MTIME_BASE))
/**@}*/
/**********************************************************************//**
* @name IO Device: Primary/Secondary Universal Asynchronous Receiver and Transmitter (UART0 / UART1)
**************************************************************************/
/**@{*/
/** UART module prototype */
typedef volatile struct __attribute__((packed,aligned(4))) {
uint32_t CTRL; /**< offset 0: control register (#NEORV32_UART_CTRL_enum) */
uint32_t DATA; /**< offset 4: data register */
} neorv32_uart_t;
/** UART0 module base address */
#define NEORV32_UART0_BASE (0xFFFFFFA0U)
/** UART0 module hardware access (#neorv32_uart_t) */
#define NEORV32_UART0 ((neorv32_uart_t*) (NEORV32_UART0_BASE))
/** UART1 module base address */
#define NEORV32_UART1_BASE (0xFFFFFFD0U)
/** UART1 module hardware access (#neorv32_uart_t) */
#define NEORV32_UART1 ((neorv32_uart_t*) (NEORV32_UART1_BASE))
/** UART control register bits */
enum NEORV32_UART_CTRL_enum {
UART_CTRL_EN = 0, /**< UART control register(0) (r/w): UART global enable */
UART_CTRL_SIM_MODE = 1, /**< UART control register(1) (r/w): Simulation output override enable */
UART_CTRL_HWFC_EN = 2, /**< UART control register(2) (r/w): Enable RTS/CTS hardware flow-control */
UART_CTRL_PRSC0 = 3, /**< UART control register(3) (r/w): clock prescaler select bit 0 */
UART_CTRL_PRSC1 = 4, /**< UART control register(4) (r/w): clock prescaler select bit 1 */
UART_CTRL_PRSC2 = 5, /**< UART control register(5) (r/w): clock prescaler select bit 2 */
UART_CTRL_BAUD0 = 6, /**< UART control register(6) (r/w): BAUD rate divisor, bit 0 */
UART_CTRL_BAUD1 = 7, /**< UART control register(7) (r/w): BAUD rate divisor, bit 1 */
UART_CTRL_BAUD2 = 8, /**< UART control register(8) (r/w): BAUD rate divisor, bit 2 */
UART_CTRL_BAUD3 = 9, /**< UART control register(9) (r/w): BAUD rate divisor, bit 3 */
UART_CTRL_BAUD4 = 10, /**< UART control register(10) (r/w): BAUD rate divisor, bit 4 */
UART_CTRL_BAUD5 = 11, /**< UART control register(11) (r/w): BAUD rate divisor, bit 5 */
UART_CTRL_BAUD6 = 12, /**< UART control register(12) (r/w): BAUD rate divisor, bit 6 */
UART_CTRL_BAUD7 = 13, /**< UART control register(13) (r/w): BAUD rate divisor, bit 7 */
UART_CTRL_BAUD8 = 14, /**< UART control register(14) (r/w): BAUD rate divisor, bit 8 */
UART_CTRL_BAUD9 = 15, /**< UART control register(15) (r/w): BAUD rate divisor, bit 9 */
UART_CTRL_RX_NEMPTY = 16, /**< UART control register(16) (r/-): RX FIFO not empty */
UART_CTRL_RX_HALF = 17, /**< UART control register(17) (r/-): RX FIFO at least half-full */
UART_CTRL_RX_FULL = 18, /**< UART control register(18) (r/-): RX FIFO full */
UART_CTRL_TX_EMPTY = 19, /**< UART control register(19) (r/-): TX FIFO empty */
UART_CTRL_TX_NHALF = 20, /**< UART control register(20) (r/-): TX FIFO not at least half-full */
UART_CTRL_TX_FULL = 21, /**< UART control register(21) (r/-): TX FIFO full */
UART_CTRL_IRQ_RX_NEMPTY = 22, /**< UART control register(22) (r/w): Fire IRQ if RX FIFO not empty */
UART_CTRL_IRQ_RX_HALF = 23, /**< UART control register(23) (r/w): Fire IRQ if RX FIFO at least half-full */
UART_CTRL_IRQ_RX_FULL = 24, /**< UART control register(24) (r/w): Fire IRQ if RX FIFO full */
UART_CTRL_IRQ_TX_EMPTY = 25, /**< UART control register(25) (r/w): Fire IRQ if TX FIFO empty */
UART_CTRL_IRQ_TX_NHALF = 26, /**< UART control register(26) (r/w): Fire IRQ if TX FIFO not at least half-full */
UART_CTRL_RX_OVER = 30, /**< UART control register(30) (r/-): RX FIFO overflow */
UART_CTRL_TX_BUSY = 31 /**< UART control register(31) (r/-): Transmitter busy or TX FIFO not empty */
};
/**@}*/
/**********************************************************************//**
* @name IO Device: Serial Peripheral Interface Controller (SPI)
**************************************************************************/
/**@{*/
/** SPI module prototype */
typedef volatile struct __attribute__((packed,aligned(4))) {
uint32_t CTRL; /**< offset 0: control register (#NEORV32_SPI_CTRL_enum) */
uint32_t DATA; /**< offset 4: data register */
} neorv32_spi_t;
/** SPI module base address */
#define NEORV32_SPI_BASE (0xFFFFFFA8U)
/** SPI module hardware access (#neorv32_spi_t) */
#define NEORV32_SPI ((neorv32_spi_t*) (NEORV32_SPI_BASE))
/** SPI control register bits */
enum NEORV32_SPI_CTRL_enum {
SPI_CTRL_EN = 0, /**< SPI control register(0) (r/w): SPI unit enable */
SPI_CTRL_CPHA = 1, /**< SPI control register(1) (r/w): Clock phase */
SPI_CTRL_CPOL = 2, /**< SPI control register(2) (r/w): Clock polarity */
SPI_CTRL_CS_SEL0 = 3, /**< SPI control register(3) (r/w): Direct chip select bit 1 */
SPI_CTRL_CS_SEL1 = 4, /**< SPI control register(4) (r/w): Direct chip select bit 2 */
SPI_CTRL_CS_SEL2 = 5, /**< SPI control register(5) (r/w): Direct chip select bit 2 */
SPI_CTRL_CS_EN = 6, /**< SPI control register(6) (r/w): Chip select enable (selected CS line output is low when set) */
SPI_CTRL_PRSC0 = 7, /**< SPI control register(7) (r/w): Clock prescaler select bit 0 */
SPI_CTRL_PRSC1 = 8, /**< SPI control register(8) (r/w): Clock prescaler select bit 1 */
SPI_CTRL_PRSC2 = 9, /**< SPI control register(9) (r/w): Clock prescaler select bit 2 */
SPI_CTRL_CDIV0 = 10, /**< SPI control register(10) (r/w): Clock divider bit 0 */
SPI_CTRL_CDIV1 = 11, /**< SPI control register(11) (r/w): Clock divider bit 1 */
SPI_CTRL_CDIV2 = 12, /**< SPI control register(12) (r/w): Clock divider bit 2 */
SPI_CTRL_CDIV3 = 13, /**< SPI control register(13) (r/w): Clock divider bit 3 */
SPI_CTRL_RX_AVAIL = 16, /**< SPI control register(16) (r/-): RX FIFO data available (RX FIFO not empty) */
SPI_CTRL_TX_EMPTY = 17, /**< SPI control register(17) (r/-): TX FIFO empty */
SPI_CTRL_TX_NHALF = 18, /**< SPI control register(18) (r/-): TX FIFO not at least half full */
SPI_CTRL_TX_FULL = 19, /**< SPI control register(19) (r/-): TX FIFO full */
SPI_CTRL_IRQ_RX_AVAIL = 20, /**< SPI control register(20) (r/w): Fire IRQ if RX FIFO data available (RX FIFO not empty) */
SPI_CTRL_IRQ_TX_EMPTY = 21, /**< SPI control register(21) (r/w): Fire IRQ if TX FIFO empty */
SPI_CTRL_IRQ_TX_HALF = 22, /**< SPI control register(22) (r/w): Fire IRQ if TX FIFO not at least half full */
SPI_CTRL_FIFO_LSB = 23, /**< SPI control register(23) (r/-): log2(FIFO size), lsb */
SPI_CTRL_FIFO_MSB = 26, /**< SPI control register(26) (r/-): log2(FIFO size), msb */
SPI_CTRL_BUSY = 31 /**< SPI control register(31) (r/-): SPI busy flag */
};
/**@}*/
/**********************************************************************//**
* @name IO Device: Two-Wire Interface Controller (TWI)
**************************************************************************/
/**@{*/
/** TWI module prototype */
typedef volatile struct __attribute__((packed,aligned(4))) {
uint32_t CTRL; /**< offset 0: control register (#NEORV32_TWI_CTRL_enum) */
uint32_t DATA; /**< offset 4: data register (#NEORV32_TWI_DATA_enum) */
} neorv32_twi_t;
/** TWI module base address */
#define NEORV32_TWI_BASE (0xFFFFFFB0U)
/** TWI module hardware access (#neorv32_twi_t) */
#define NEORV32_TWI ((neorv32_twi_t*) (NEORV32_TWI_BASE))
/** TWI control register bits */
enum NEORV32_TWI_CTRL_enum {
TWI_CTRL_EN = 0, /**< TWI control register(0) (r/w): TWI enable */
TWI_CTRL_START = 1, /**< TWI control register(1) (-/w): Generate START condition, auto-clears */
TWI_CTRL_STOP = 2, /**< TWI control register(2) (-/w): Generate STOP condition, auto-clears */
TWI_CTRL_MACK = 3, /**< TWI control register(3) (r/w): Generate ACK by controller for each transmission */
TWI_CTRL_CSEN = 4, /**< TWI control register(4) (r/w): Allow clock stretching when set */
TWI_CTRL_PRSC0 = 5, /**< TWI control register(5) (r/w): Clock prescaler select bit 0 */
TWI_CTRL_PRSC1 = 6, /**< TWI control register(6) (r/w): Clock prescaler select bit 1 */
TWI_CTRL_PRSC2 = 7, /**< TWI control register(7) (r/w): Clock prescaler select bit 2 */
TWI_CTRL_CDIV0 = 8, /**< TWI control register(8) (r/w): Clock divider bit 0 */
TWI_CTRL_CDIV1 = 9, /**< TWI control register(9) (r/w): Clock divider bit 1 */
TWI_CTRL_CDIV2 = 10, /**< TWI control register(10) (r/w): Clock divider bit 2 */
TWI_CTRL_CDIV3 = 11, /**< TWI control register(11) (r/w): Clock divider bit 3 */
TWI_CTRL_CLAIMED = 29, /**< TWI control register(29) (r/-): Set if the TWI bus is currently claimed by any controller */
TWI_CTRL_ACK = 30, /**< TWI control register(30) (r/-): ACK received when set */
TWI_CTRL_BUSY = 31 /**< TWI control register(31) (r/-): Transfer in progress, busy flag */
};
/** TWI receive/transmit data register bits */
enum NEORV32_TWI_DATA_enum {
TWI_DATA_LSB = 0, /**< TWI data register(0) (r/w): Receive/transmit data (8-bit) LSB */
TWI_DATA_MSB = 7 /**< TWI data register(7) (r/w): Receive/transmit data (8-bit) MSB */
};
/**@}*/
/**********************************************************************//**
* @name IO Device: True Random Number Generator (TRNG)
**************************************************************************/
/**@{*/
/** TRNG module prototype */
typedef volatile struct __attribute__((packed,aligned(4))) {
uint32_t CTRL; /**< offset 0: control register (#NEORV32_TRNG_CTRL_enum) */
} neorv32_trng_t;
/** TRNG module base address */
#define NEORV32_TRNG_BASE (0xFFFFFFB8U)
/** TRNG module hardware access (#neorv32_trng_t) */
#define NEORV32_TRNG ((neorv32_trng_t*) (NEORV32_TRNG_BASE))
/** TRNG control/data register bits */
enum NEORV32_TRNG_CTRL_enum {
TRNG_CTRL_DATA_LSB = 0, /**< TRNG data/control register(0) (r/-): Random data byte LSB */
TRNG_CTRL_DATA_MSB = 7, /**< TRNG data/control register(7) (r/-): Random data byte MSB */
TRNG_CTRL_FIFO_CLR = 28, /**< TRNG data/control register(28) (-/w): Clear data FIFO (auto clears) */
TRNG_CTRL_SIM_MODE = 29, /**< TRNG data/control register(29) (r/-): PRNG mode (simulation mode) */
TRNG_CTRL_EN = 30, /**< TRNG data/control register(30) (r/w): TRNG enable */
TRNG_CTRL_VALID = 31 /**< TRNG data/control register(31) (r/-): Random data output valid */
};
/**@}*/
/**********************************************************************//**
* @name IO Device: Watchdog Timer (WDT)
**************************************************************************/
/**@{*/
/** WDT module prototype */
typedef volatile struct __attribute__((packed,aligned(4))) {
uint32_t CTRL; /**< offset 0: control register (#NEORV32_WDT_CTRL_enum) */
} neorv32_wdt_t;
/** WDT module base address */
#define NEORV32_WDT_BASE (0xFFFFFFBCU)
/** WDT module hardware access (#neorv32_wdt_t) */
#define NEORV32_WDT ((neorv32_wdt_t*) (NEORV32_WDT_BASE))
/** WDT control register bits */
enum NEORV32_WDT_CTRL_enum {
WDT_CTRL_EN = 0, /**< WDT control register(0) (r/w): Watchdog enable */
WDT_CTRL_LOCK = 1, /**< WDT control register(1) (r/w): Lock write access to control register, clears on reset only */
WDT_CTRL_DBEN = 2, /**< WDT control register(2) (r/w): Allow WDT to continue operation even when CPU is in debug mode */
WDT_CTRL_SEN = 3, /**< WDT control register(3) (r/w): Allow WDT to continue operation even when CPU is in sleep mode */
WDT_CTRL_RESET = 4, /**< WDT control register(4) (-/w): Reset WDT counter when set, auto-clears */
WDT_CTRL_RCAUSE = 5, /**< WDT control register(5) (r/-): Cause of last system reset: 0=external reset, 1=watchdog */
WDT_CTRL_TIMEOUT_LSB = 8, /**< WDT control register(8) (r/w): Timeout value, LSB */
WDT_CTRL_TIMEOUT_MSB = 31 /**< WDT control register(31) (r/w): Timeout value, MSB */
};
/**@}*/
/**********************************************************************//**
* @name IO Device: General Purpose Input/Output Port Unit (GPIO)
**************************************************************************/
/**@{*/
/** GPIO module base address */
#define NEORV32_GPIO_BASE (0xFFFFFFC0U)
/**@}*/
/**********************************************************************//**
* @name IO Device: Smart LED Hardware Interface (NEOLED)
**************************************************************************/
/**@{*/
/** NEOLED module prototype */
typedef volatile struct __attribute__((packed,aligned(4))) {
uint32_t CTRL; /**< offset 0: control register */
uint32_t DATA; /**< offset 4: data register (#NEORV32_NEOLED_CTRL_enum) */
} neorv32_neoled_t;
/** NEOLED module base address */
#define NEORV32_NEOLED_BASE (0xFFFFFFD8U)
/** NEOLED module hardware access (#neorv32_neoled_t) */
#define NEORV32_NEOLED ((neorv32_neoled_t*) (NEORV32_NEOLED_BASE))
/** NEOLED control register bits */
enum NEORV32_NEOLED_CTRL_enum {
NEOLED_CTRL_EN = 0, /**< NEOLED control register(0) (r/w): NEOLED global enable */
NEOLED_CTRL_MODE = 1, /**< NEOLED control register(1) (r/w): TX mode (0=24-bit, 1=32-bit) */
NEOLED_CTRL_STROBE = 2, /**< NEOLED control register(2) (r/w): Strobe (0=send normal data, 1=send RESET command on data write) */
NEOLED_CTRL_PRSC0 = 3, /**< NEOLED control register(3) (r/w): Clock prescaler select bit 0 (pulse-clock speed select) */
NEOLED_CTRL_PRSC1 = 4, /**< NEOLED control register(4) (r/w): Clock prescaler select bit 1 (pulse-clock speed select) */
NEOLED_CTRL_PRSC2 = 5, /**< NEOLED control register(5) (r/w): Clock prescaler select bit 2 (pulse-clock speed select) */
NEOLED_CTRL_BUFS_0 = 6, /**< NEOLED control register(6) (r/-): log2(tx buffer size) bit 0 */
NEOLED_CTRL_BUFS_1 = 7, /**< NEOLED control register(7) (r/-): log2(tx buffer size) bit 1 */
NEOLED_CTRL_BUFS_2 = 8, /**< NEOLED control register(8) (r/-): log2(tx buffer size) bit 2 */
NEOLED_CTRL_BUFS_3 = 9, /**< NEOLED control register(9) (r/-): log2(tx buffer size) bit 3 */
NEOLED_CTRL_T_TOT_0 = 10, /**< NEOLED control register(10) (r/w): pulse-clock ticks per total period bit 0 */
NEOLED_CTRL_T_TOT_1 = 11, /**< NEOLED control register(11) (r/w): pulse-clock ticks per total period bit 1 */
NEOLED_CTRL_T_TOT_2 = 12, /**< NEOLED control register(12) (r/w): pulse-clock ticks per total period bit 2 */
NEOLED_CTRL_T_TOT_3 = 13, /**< NEOLED control register(13) (r/w): pulse-clock ticks per total period bit 3 */
NEOLED_CTRL_T_TOT_4 = 14, /**< NEOLED control register(14) (r/w): pulse-clock ticks per total period bit 4 */
NEOLED_CTRL_T_ZERO_H_0 = 15, /**< NEOLED control register(15) (r/w): pulse-clock ticks per ZERO high-time bit 0 */
NEOLED_CTRL_T_ZERO_H_1 = 16, /**< NEOLED control register(16) (r/w): pulse-clock ticks per ZERO high-time bit 1 */
NEOLED_CTRL_T_ZERO_H_2 = 17, /**< NEOLED control register(17) (r/w): pulse-clock ticks per ZERO high-time bit 2 */
NEOLED_CTRL_T_ZERO_H_3 = 18, /**< NEOLED control register(18) (r/w): pulse-clock ticks per ZERO high-time bit 3 */
NEOLED_CTRL_T_ZERO_H_4 = 19, /**< NEOLED control register(19) (r/w): pulse-clock ticks per ZERO high-time bit 4 */
NEOLED_CTRL_T_ONE_H_0 = 20, /**< NEOLED control register(20) (r/w): pulse-clock ticks per ONE high-time bit 0 */
NEOLED_CTRL_T_ONE_H_1 = 21, /**< NEOLED control register(21) (r/w): pulse-clock ticks per ONE high-time bit 1 */
NEOLED_CTRL_T_ONE_H_2 = 22, /**< NEOLED control register(22) (r/w): pulse-clock ticks per ONE high-time bit 2 */
NEOLED_CTRL_T_ONE_H_3 = 23, /**< NEOLED control register(23) (r/w): pulse-clock ticks per ONE high-time bit 3 */
NEOLED_CTRL_T_ONE_H_4 = 24, /**< NEOLED control register(24) (r/w): pulse-clock ticks per ONE high-time bit 4 */
NEOLED_CTRL_IRQ_CONF = 27, /**< NEOLED control register(27) (r/w): TX FIFO interrupt: 1=IRQ if FIFO is empty, 1=IRQ if FIFO is less than half-full */
NEOLED_CTRL_TX_EMPTY = 28, /**< NEOLED control register(28) (r/-): TX FIFO is empty */
NEOLED_CTRL_TX_HALF = 29, /**< NEOLED control register(29) (r/-): TX FIFO is at least half-full */
NEOLED_CTRL_TX_FULL = 30, /**< NEOLED control register(30) (r/-): TX FIFO is full */
NEOLED_CTRL_TX_BUSY = 31 /**< NEOLED control register(31) (r/-): busy flag */
};
/**@}*/
/**********************************************************************//**
* @name IO Device: System Configuration Information Memory (SYSINFO)
**************************************************************************/
/**@{*/
/** SYSINFO module prototype - whole module is read-only */
typedef volatile struct __attribute__((packed,aligned(4))) {
const uint32_t CLK; /**< offset 0: clock speed in Hz */
const uint32_t CUSTOM_ID; /**< offset 4: custom user-defined ID (via top generic) */
const uint32_t SOC; /**< offset 8: SoC features (#NEORV32_SYSINFO_SOC_enum) */
const uint32_t CACHE; /**< offset 12: cache configuration (#NEORV32_SYSINFO_CACHE_enum) */
const uint32_t ISPACE_BASE; /**< offset 16: instruction memory address space base */
const uint32_t DSPACE_BASE; /**< offset 20: data memory address space base */
const uint32_t IMEM_SIZE; /**< offset 24: internal instruction memory (IMEM) size in bytes */
const uint32_t DMEM_SIZE; /**< offset 28: internal data memory (DMEM) size in bytes */
} neorv32_sysinfo_t;
/** SYSINFO module base address */
#define NEORV32_SYSINFO_BASE (0xFFFFFFE0U)
/** SYSINFO module hardware access (#neorv32_sysinfo_t) */
#define NEORV32_SYSINFO ((neorv32_sysinfo_t*) (NEORV32_SYSINFO_BASE))
/** NEORV32_SYSINFO->SOC (r/-): Implemented processor devices/features */
enum NEORV32_SYSINFO_SOC_enum {
SYSINFO_SOC_BOOTLOADER = 0, /**< SYSINFO_FEATURES (0) (r/-): Bootloader implemented when 1 (via INT_BOOTLOADER_EN generic) */
SYSINFO_SOC_MEM_EXT = 1, /**< SYSINFO_FEATURES (1) (r/-): External bus interface implemented when 1 (via MEM_EXT_EN generic) */
SYSINFO_SOC_MEM_INT_IMEM = 2, /**< SYSINFO_FEATURES (2) (r/-): Processor-internal instruction memory implemented when 1 (via MEM_INT_IMEM_EN generic) */
SYSINFO_SOC_MEM_INT_DMEM = 3, /**< SYSINFO_FEATURES (3) (r/-): Processor-internal data memory implemented when 1 (via MEM_INT_DMEM_EN generic) */
SYSINFO_SOC_MEM_EXT_ENDIAN = 4, /**< SYSINFO_FEATURES (4) (r/-): External bus interface uses BIG-endian byte-order when 1 (via MEM_EXT_BIG_ENDIAN generic) */
SYSINFO_SOC_ICACHE = 5, /**< SYSINFO_FEATURES (5) (r/-): Processor-internal instruction cache implemented when 1 (via ICACHE_EN generic) */
SYSINFO_SOC_IS_SIM = 13, /**< SYSINFO_FEATURES (13) (r/-): Set during simulation (not guaranteed) */
SYSINFO_SOC_OCD = 14, /**< SYSINFO_FEATURES (14) (r/-): On-chip debugger implemented when 1 (via ON_CHIP_DEBUGGER_EN generic) */
SYSINFO_SOC_IO_GPIO = 16, /**< SYSINFO_FEATURES (16) (r/-): General purpose input/output port unit implemented when 1 (via IO_GPIO_EN generic) */
SYSINFO_SOC_IO_MTIME = 17, /**< SYSINFO_FEATURES (17) (r/-): Machine system timer implemented when 1 (via IO_MTIME_EN generic) */
SYSINFO_SOC_IO_UART0 = 18, /**< SYSINFO_FEATURES (18) (r/-): Primary universal asynchronous receiver/transmitter 0 implemented when 1 (via IO_UART0_EN generic) */
SYSINFO_SOC_IO_SPI = 19, /**< SYSINFO_FEATURES (19) (r/-): Serial peripheral interface implemented when 1 (via IO_SPI_EN generic) */
SYSINFO_SOC_IO_TWI = 20, /**< SYSINFO_FEATURES (20) (r/-): Two-wire interface implemented when 1 (via IO_TWI_EN generic) */
SYSINFO_SOC_IO_PWM = 21, /**< SYSINFO_FEATURES (21) (r/-): Pulse-width modulation unit implemented when 1 (via IO_PWM_EN generic) */
SYSINFO_SOC_IO_WDT = 22, /**< SYSINFO_FEATURES (22) (r/-): Watchdog timer implemented when 1 (via IO_WDT_EN generic) */
SYSINFO_SOC_IO_CFS = 23, /**< SYSINFO_FEATURES (23) (r/-): Custom functions subsystem implemented when 1 (via IO_CFS_EN generic) */
SYSINFO_SOC_IO_TRNG = 24, /**< SYSINFO_FEATURES (24) (r/-): True random number generator implemented when 1 (via IO_TRNG_EN generic) */
SYSINFO_SOC_IO_SDI = 25, /**< SYSINFO_FEATURES (25) (r/-): Serial data interface implemented when 1 (via IO_SDI_EN generic) */
SYSINFO_SOC_IO_UART1 = 26, /**< SYSINFO_FEATURES (26) (r/-): Secondary universal asynchronous receiver/transmitter 1 implemented when 1 (via IO_UART1_EN generic) */
SYSINFO_SOC_IO_NEOLED = 27, /**< SYSINFO_FEATURES (27) (r/-): NeoPixel-compatible smart LED interface implemented when 1 (via IO_NEOLED_EN generic) */
SYSINFO_SOC_IO_XIRQ = 28, /**< SYSINFO_FEATURES (28) (r/-): External interrupt controller implemented when 1 (via XIRQ_NUM_IO generic) */
SYSINFO_SOC_IO_GPTMR = 29, /**< SYSINFO_FEATURES (29) (r/-): General purpose timer implemented when 1 (via IO_GPTMR_EN generic) */
SYSINFO_SOC_IO_XIP = 30, /**< SYSINFO_FEATURES (30) (r/-): Execute in place module implemented when 1 (via IO_XIP_EN generic) */
SYSINFO_SOC_IO_ONEWIRE = 31 /**< SYSINFO_FEATURES (31) (r/-): 1-wire interface controller implemented when 1 (via IO_ONEWIRE_EN generic) */
};
/** NEORV32_SYSINFO->CACHE (r/-): Cache configuration */
enum NEORV32_SYSINFO_CACHE_enum {
SYSINFO_CACHE_IC_BLOCK_SIZE_0 = 0, /**< SYSINFO_CACHE (0) (r/-): i-cache: log2(Block size in bytes), bit 0 (via ICACHE_BLOCK_SIZE generic) */
SYSINFO_CACHE_IC_BLOCK_SIZE_1 = 1, /**< SYSINFO_CACHE (1) (r/-): i-cache: log2(Block size in bytes), bit 1 (via ICACHE_BLOCK_SIZE generic) */
SYSINFO_CACHE_IC_BLOCK_SIZE_2 = 2, /**< SYSINFO_CACHE (2) (r/-): i-cache: log2(Block size in bytes), bit 2 (via ICACHE_BLOCK_SIZE generic) */
SYSINFO_CACHE_IC_BLOCK_SIZE_3 = 3, /**< SYSINFO_CACHE (3) (r/-): i-cache: log2(Block size in bytes), bit 3 (via ICACHE_BLOCK_SIZE generic) */
SYSINFO_CACHE_IC_NUM_BLOCKS_0 = 4, /**< SYSINFO_CACHE (4) (r/-): i-cache: log2(Number of cache blocks/pages/lines), bit 0 (via ICACHE_NUM_BLOCKS generic) */
SYSINFO_CACHE_IC_NUM_BLOCKS_1 = 5, /**< SYSINFO_CACHE (5) (r/-): i-cache: log2(Number of cache blocks/pages/lines), bit 1 (via ICACHE_NUM_BLOCKS generic) */
SYSINFO_CACHE_IC_NUM_BLOCKS_2 = 6, /**< SYSINFO_CACHE (6) (r/-): i-cache: log2(Number of cache blocks/pages/lines), bit 2 (via ICACHE_NUM_BLOCKS generic) */
SYSINFO_CACHE_IC_NUM_BLOCKS_3 = 7, /**< SYSINFO_CACHE (7) (r/-): i-cache: log2(Number of cache blocks/pages/lines), bit 3 (via ICACHE_NUM_BLOCKS generic) */
SYSINFO_CACHE_IC_ASSOCIATIVITY_0 = 8, /**< SYSINFO_CACHE (8) (r/-): i-cache: log2(associativity), bit 0 (via ICACHE_ASSOCIATIVITY generic) */
SYSINFO_CACHE_IC_ASSOCIATIVITY_1 = 9, /**< SYSINFO_CACHE (9) (r/-): i-cache: log2(associativity), bit 1 (via ICACHE_ASSOCIATIVITY generic) */
SYSINFO_CACHE_IC_ASSOCIATIVITY_2 = 10, /**< SYSINFO_CACHE (10) (r/-): i-cache: log2(associativity), bit 2 (via ICACHE_ASSOCIATIVITY generic) */
SYSINFO_CACHE_IC_ASSOCIATIVITY_3 = 11, /**< SYSINFO_CACHE (11) (r/-): i-cache: log2(associativity), bit 3 (via ICACHE_ASSOCIATIVITY generic) */
SYSINFO_CACHE_IC_REPLACEMENT_0 = 12, /**< SYSINFO_CACHE (12) (r/-): i-cache: replacement policy (0001 = LRU if associativity > 0) bit 0 */
SYSINFO_CACHE_IC_REPLACEMENT_1 = 13, /**< SYSINFO_CACHE (13) (r/-): i-cache: replacement policy (0001 = LRU if associativity > 0) bit 1 */
SYSINFO_CACHE_IC_REPLACEMENT_2 = 14, /**< SYSINFO_CACHE (14) (r/-): i-cache: replacement policy (0001 = LRU if associativity > 0) bit 2 */
SYSINFO_CACHE_IC_REPLACEMENT_3 = 15, /**< SYSINFO_CACHE (15) (r/-): i-cache: replacement policy (0001 = LRU if associativity > 0) bit 3 */
};
/**@}*/
@ -1327,11 +712,13 @@ enum NEORV32_SYSINFO_SOC_enum {
// cpu core
#include "neorv32_cpu.h"
#include "neorv32_cpu_cfu.h"
#include "neorv32_dm.h"
// neorv32 runtime environment
#include "neorv32_rte.h"
// io/peripheral devices
#include "neorv32_buskeeper.h"
#include "neorv32_cfs.h"
#include "neorv32_gpio.h"
#include "neorv32_gptmr.h"
@ -1341,6 +728,7 @@ enum NEORV32_SYSINFO_SOC_enum {
#include "neorv32_pwm.h"
#include "neorv32_sdi.h"
#include "neorv32_spi.h"
#include "neorv32_sysinfo.h"
#include "neorv32_trng.h"
#include "neorv32_twi.h"
#include "neorv32_uart.h"

65
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@ -0,0 +1,65 @@
// #################################################################################################
// # << NEORV32: neorv32_buskeeper.h - Bus Monitor (BUSKEEPER) HW Driver (stub) >> #
// # ********************************************************************************************* #
// # BSD 3-Clause License #
// # #
// # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
// # #
// # Redistribution and use in source and binary forms, with or without modification, are #
// # permitted provided that the following conditions are met: #
// # #
// # 1. Redistributions of source code must retain the above copyright notice, this list of #
// # conditions and the following disclaimer. #
// # #
// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
// # conditions and the following disclaimer in the documentation and/or other materials #
// # provided with the distribution. #
// # #
// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
// # endorse or promote products derived from this software without specific prior written #
// # permission. #
// # #
// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
// # OF THE POSSIBILITY OF SUCH DAMAGE. #
// # ********************************************************************************************* #
// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
// #################################################################################################
/**********************************************************************//**
* @file neorv32_buskeeper.h
* @brief Bus Monitor (BUSKEEPER) HW driver header file.
**************************************************************************/
#ifndef neorv32_buskeeper_h
#define neorv32_buskeeper_h
/**********************************************************************//**
* @name IO Device: Bus Monitor (BUSKEEPER)
**************************************************************************/
/**@{*/
/** BUSKEEPER module prototype */
typedef volatile struct __attribute__((packed,aligned(4))) {
uint32_t CTRL; /**< offset 0: control register (#NEORV32_BUSKEEPER_CTRL_enum) */
const uint32_t reserved ; /**< offset 4: reserved */
} neorv32_buskeeper_t;
/** BUSKEEPER module hardware access (#neorv32_buskeeper_t) */
#define NEORV32_BUSKEEPER ((neorv32_buskeeper_t*) (NEORV32_BUSKEEPER_BASE))
/** BUSKEEPER control/data register bits */
enum NEORV32_BUSKEEPER_CTRL_enum {
BUSKEEPER_ERR_TYPE = 0, /**< BUSKEEPER control register( 0) (r/-): Bus error type: 0=device error, 1=access timeout */
BUSKEEPER_ERR_FLAG = 31 /**< BUSKEEPER control register(31) (r/-): Sticky error flag, clears after read or write access */
};
/**@}*/
#endif // neorv32_buskeeper_h

18
sw/lib/include/neorv32_cfs.h
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@ -1,5 +1,5 @@
// #################################################################################################
// # << NEORV32: neorv32_cfs.h - Custom Functions Subsystem (CFS)) HW Driver (stub) >> #
// # << NEORV32: neorv32_cfs.h - Custom Functions Subsystem (CFS) HW Driver (stub) >> #
// # ********************************************************************************************* #
// # BSD 3-Clause License #
// # #
@ -35,7 +35,7 @@
/**********************************************************************//**
* @file neorv32_cfs.h
* @brief Custom Functions Subsystem (CFS)) HW driver header file.
* @brief Custom Functions Subsystem (CFS) HW driver header file.
*
* @warning There are no "real" CFS driver functions available here, because these functions are defined by the actual hardware.
* @warning The CFS designer has to provide the actual driver functions.
@ -46,6 +46,20 @@
#ifndef neorv32_cfs_h
#define neorv32_cfs_h
/**********************************************************************//**
* @name IO Device: Custom Functions Subsystem (CFS)
**************************************************************************/
/**@{*/
/** CFS module prototype */
typedef volatile struct __attribute__((packed,aligned(4))) {
uint32_t REG[64]; /**< offset 4*0..4*63: CFS register 0..63, user-defined */
} neorv32_cfs_t;
/** CFS module hardware access (#neorv32_cfs_t) */
#define NEORV32_CFS ((neorv32_cfs_t*) (NEORV32_CFS_BASE))
/**@}*/
// prototypes
int neorv32_cfs_available(void);

64
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@ -0,0 +1,64 @@
// #################################################################################################
// # << NEORV32: neorv32_dm.h - On-Chip Debugger HW Driver (Header) >> #
// # ********************************************************************************************* #
// # BSD 3-Clause License #
// # #
// # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
// # #
// # Redistribution and use in source and binary forms, with or without modification, are #
// # permitted provided that the following conditions are met: #
// # #
// # 1. Redistributions of source code must retain the above copyright notice, this list of #
// # conditions and the following disclaimer. #
// # #
// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
// # conditions and the following disclaimer in the documentation and/or other materials #
// # provided with the distribution. #
// # #
// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
// # endorse or promote products derived from this software without specific prior written #
// # permission. #
// # #
// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
// # OF THE POSSIBILITY OF SUCH DAMAGE. #
// # ********************************************************************************************* #
// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
// #################################################################################################
/**********************************************************************//**
* @file neorv32_dm.h
* @brief On-Chip Debugger (should NOT be used by application software at all!)
**************************************************************************/
#ifndef neorv32_dm_h
#define neorv32_dm_h
// #################################################################################################
// On-Chip Debugger (should NOT be used by application software at all!)
// #################################################################################################
/**@{*/
/** on-chip debugger - debug module prototype */
typedef volatile struct __attribute__((packed,aligned(4))) {
const uint32_t CODE[16]; /**< offset 0: park loop code ROM (r/-) */
const uint32_t PBUF[4]; /**< offset 64: program buffer (r/-) */
const uint32_t reserved1[12]; /**< reserved */
uint32_t DATA; /**< offset 128: data exchange register (r/w) */
const uint32_t reserved2[15]; /**< reserved */
uint32_t SREG; /**< offset 192: control and status register (r/w) */
const uint32_t reserved3[15]; /**< reserved */
} neorv32_dm_t;
/** on-chip debugger debug module hardware access (#neorv32_dm_t) */
#define NEORV32_DM ((neorv32_dm_t*) (NEORV32_DM_BASE))
/**@}*/
#endif // neorv32_dm_h

26
sw/lib/include/neorv32_gptmr.h
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@ -43,6 +43,32 @@
#ifndef neorv32_gptmr_h
#define neorv32_gptmr_h
/**********************************************************************//**
* @name IO Device: General Purpose Timer (GPTMR)
**************************************************************************/
/**@{*/
/** GPTMR module prototype */
typedef volatile struct __attribute__((packed,aligned(4))) {
uint32_t CTRL; /**< offset 0: control register (#NEORV32_GPTMR_CTRL_enum) */
uint32_t THRES; /**< offset 4: threshold register */
uint32_t COUNT; /**< offset 8: counter register */
const uint32_t reserved; /**< offset 12: reserved */
} neorv32_gptmr_t;
/** GPTMR module hardware access (#neorv32_gptmr_t) */
#define NEORV32_GPTMR ((neorv32_gptmr_t*) (NEORV32_GPTMR_BASE))
/** GPTMR control/data register bits */
enum NEORV32_GPTMR_CTRL_enum {
GPTMR_CTRL_EN = 0, /**< GPTIMR control register(0) (r/w): Timer unit enable */
GPTMR_CTRL_PRSC0 = 1, /**< GPTIMR control register(1) (r/w): Clock prescaler select bit 0 */
GPTMR_CTRL_PRSC1 = 2, /**< GPTIMR control register(2) (r/w): Clock prescaler select bit 1 */
GPTMR_CTRL_PRSC2 = 3, /**< GPTIMR control register(3) (r/w): Clock prescaler select bit 2 */
GPTMR_CTRL_MODE = 4 /**< GPTIMR control register(4) (r/w): Timer mode: 0=single-shot mode, 1=continuous mode */
};
/**@}*/
// prototypes
int neorv32_gptmr_available(void);
void neorv32_gptmr_setup(int prsc, int mode, uint32_t threshold);

17
sw/lib/include/neorv32_mtime.h
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@ -43,6 +43,23 @@
#ifndef neorv32_mtime_h
#define neorv32_mtime_h
/**********************************************************************//**
* @name IO Device: Machine System Timer (MTIME)
**************************************************************************/
/**@{*/
/** MTIME module prototype */
typedef volatile struct __attribute__((packed,aligned(4))) {
uint32_t TIME_LO; /**< offset 0: time register low word */
uint32_t TIME_HI; /**< offset 4: time register high word */
uint32_t TIMECMP_LO; /**< offset 8: compare register low word */
uint32_t TIMECMP_HI; /**< offset 12: compare register high word */
} neorv32_mtime_t;
/** MTIME module hardware access (#neorv32_mtime_t) */
#define NEORV32_MTIME ((neorv32_mtime_t*) (NEORV32_MTIME_BASE))
/**@}*/
// prototypes
int neorv32_mtime_available(void);
void neorv32_mtime_set_time(uint64_t time);

54
sw/lib/include/neorv32_neoled.h
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@ -43,6 +43,60 @@
#ifndef neorv32_neoled_h
#define neorv32_neoled_h
/**********************************************************************//**
* @name IO Device: Smart LED Hardware Interface (NEOLED)
**************************************************************************/
/**@{*/
/** NEOLED module prototype */
typedef volatile struct __attribute__((packed,aligned(4))) {
uint32_t CTRL; /**< offset 0: control register */
uint32_t DATA; /**< offset 4: data register (#NEORV32_NEOLED_CTRL_enum) */
} neorv32_neoled_t;
/** NEOLED module hardware access (#neorv32_neoled_t) */
#define NEORV32_NEOLED ((neorv32_neoled_t*) (NEORV32_NEOLED_BASE))
/** NEOLED control register bits */
enum NEORV32_NEOLED_CTRL_enum {
NEOLED_CTRL_EN = 0, /**< NEOLED control register(0) (r/w): NEOLED global enable */
NEOLED_CTRL_MODE = 1, /**< NEOLED control register(1) (r/w): TX mode (0=24-bit, 1=32-bit) */
NEOLED_CTRL_STROBE = 2, /**< NEOLED control register(2) (r/w): Strobe (0=send normal data, 1=send RESET command on data write) */
NEOLED_CTRL_PRSC0 = 3, /**< NEOLED control register(3) (r/w): Clock prescaler select bit 0 (pulse-clock speed select) */
NEOLED_CTRL_PRSC1 = 4, /**< NEOLED control register(4) (r/w): Clock prescaler select bit 1 (pulse-clock speed select) */
NEOLED_CTRL_PRSC2 = 5, /**< NEOLED control register(5) (r/w): Clock prescaler select bit 2 (pulse-clock speed select) */
NEOLED_CTRL_BUFS_0 = 6, /**< NEOLED control register(6) (r/-): log2(tx buffer size) bit 0 */
NEOLED_CTRL_BUFS_1 = 7, /**< NEOLED control register(7) (r/-): log2(tx buffer size) bit 1 */
NEOLED_CTRL_BUFS_2 = 8, /**< NEOLED control register(8) (r/-): log2(tx buffer size) bit 2 */
NEOLED_CTRL_BUFS_3 = 9, /**< NEOLED control register(9) (r/-): log2(tx buffer size) bit 3 */
NEOLED_CTRL_T_TOT_0 = 10, /**< NEOLED control register(10) (r/w): pulse-clock ticks per total period bit 0 */
NEOLED_CTRL_T_TOT_1 = 11, /**< NEOLED control register(11) (r/w): pulse-clock ticks per total period bit 1 */
NEOLED_CTRL_T_TOT_2 = 12, /**< NEOLED control register(12) (r/w): pulse-clock ticks per total period bit 2 */
NEOLED_CTRL_T_TOT_3 = 13, /**< NEOLED control register(13) (r/w): pulse-clock ticks per total period bit 3 */
NEOLED_CTRL_T_TOT_4 = 14, /**< NEOLED control register(14) (r/w): pulse-clock ticks per total period bit 4 */
NEOLED_CTRL_T_ZERO_H_0 = 15, /**< NEOLED control register(15) (r/w): pulse-clock ticks per ZERO high-time bit 0 */
NEOLED_CTRL_T_ZERO_H_1 = 16, /**< NEOLED control register(16) (r/w): pulse-clock ticks per ZERO high-time bit 1 */
NEOLED_CTRL_T_ZERO_H_2 = 17, /**< NEOLED control register(17) (r/w): pulse-clock ticks per ZERO high-time bit 2 */
NEOLED_CTRL_T_ZERO_H_3 = 18, /**< NEOLED control register(18) (r/w): pulse-clock ticks per ZERO high-time bit 3 */
NEOLED_CTRL_T_ZERO_H_4 = 19, /**< NEOLED control register(19) (r/w): pulse-clock ticks per ZERO high-time bit 4 */
NEOLED_CTRL_T_ONE_H_0 = 20, /**< NEOLED control register(20) (r/w): pulse-clock ticks per ONE high-time bit 0 */
NEOLED_CTRL_T_ONE_H_1 = 21, /**< NEOLED control register(21) (r/w): pulse-clock ticks per ONE high-time bit 1 */
NEOLED_CTRL_T_ONE_H_2 = 22, /**< NEOLED control register(22) (r/w): pulse-clock ticks per ONE high-time bit 2 */
NEOLED_CTRL_T_ONE_H_3 = 23, /**< NEOLED control register(23) (r/w): pulse-clock ticks per ONE high-time bit 3 */
NEOLED_CTRL_T_ONE_H_4 = 24, /**< NEOLED control register(24) (r/w): pulse-clock ticks per ONE high-time bit 4 */
NEOLED_CTRL_IRQ_CONF = 27, /**< NEOLED control register(27) (r/w): TX FIFO interrupt: 1=IRQ if FIFO is empty, 1=IRQ if FIFO is less than half-full */
NEOLED_CTRL_TX_EMPTY = 28, /**< NEOLED control register(28) (r/-): TX FIFO is empty */
NEOLED_CTRL_TX_HALF = 29, /**< NEOLED control register(29) (r/-): TX FIFO is at least half-full */
NEOLED_CTRL_TX_FULL = 30, /**< NEOLED control register(30) (r/-): TX FIFO is full */
NEOLED_CTRL_TX_BUSY = 31 /**< NEOLED control register(31) (r/-): busy flag */
};
/**@}*/
// prototypes
int neorv32_neoled_available(void);
void neorv32_neoled_setup(uint32_t prsc, uint32_t t_total, uint32_t t_high_zero, uint32_t t_high_one, int irq_mode);

43
sw/lib/include/neorv32_onewire.h
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@ -43,6 +43,49 @@
#ifndef neorv32_onewire_h
#define neorv32_onewire_h
/**********************************************************************//**
* @name IO Device: 1-Wire Interface Controller (ONEWIRE)
**************************************************************************/
/**@{*/
/** ONEWIRE module prototype */
typedef volatile struct __attribute__((packed,aligned(4))) {
uint32_t CTRL; /**< offset 0: control register (#NEORV32_ONEWIRE_CTRL_enum) */
uint32_t DATA; /**< offset 4: transmission data register (#NEORV32_ONEWIRE_DATA_enum) */
} neorv32_onewire_t;
/** ONEWIRE module hardware access (#neorv32_onewire_t) */
#define NEORV32_ONEWIRE ((neorv32_onewire_t*) (NEORV32_ONEWIRE_BASE))
/** ONEWIRE control register bits */
enum NEORV32_ONEWIRE_CTRL_enum {
ONEWIRE_CTRL_EN = 0, /**< ONEWIRE control register(0) (r/w): ONEWIRE controller enable */
ONEWIRE_CTRL_PRSC0 = 1, /**< ONEWIRE control register(1) (r/w): Clock prescaler select bit 0 */
ONEWIRE_CTRL_PRSC1 = 2, /**< ONEWIRE control register(2) (r/w): Clock prescaler select bit 1 */
ONEWIRE_CTRL_CLKDIV0 = 3, /**< ONEWIRE control register(3) (r/w): Clock divider bit 0 */
ONEWIRE_CTRL_CLKDIV1 = 4, /**< ONEWIRE control register(4) (r/w): Clock divider bit 1 */
ONEWIRE_CTRL_CLKDIV2 = 5, /**< ONEWIRE control register(5) (r/w): Clock divider bit 2 */
ONEWIRE_CTRL_CLKDIV3 = 6, /**< ONEWIRE control register(6) (r/w): Clock divider bit 3 */
ONEWIRE_CTRL_CLKDIV4 = 7, /**< ONEWIRE control register(7) (r/w): Clock divider bit 4 */
ONEWIRE_CTRL_CLKDIV5 = 8, /**< ONEWIRE control register(8) (r/w): Clock divider bit 5 */
ONEWIRE_CTRL_CLKDIV6 = 9, /**< ONEWIRE control register(9) (r/w): Clock divider bit 6 */
ONEWIRE_CTRL_CLKDIV7 = 10, /**< ONEWIRE control register(10) (r/w): Clock divider bit 7 */
ONEWIRE_CTRL_TRIG_RST = 11, /**< ONEWIRE control register(11) (-/w): Trigger reset pulse, auto-clears */
ONEWIRE_CTRL_TRIG_BIT = 12, /**< ONEWIRE control register(12) (-/w): Trigger single-bit transmission, auto-clears */
ONEWIRE_CTRL_TRIG_BYTE = 13, /**< ONEWIRE control register(13) (-/w): Trigger full-byte transmission, auto-clears */
ONEWIRE_CTRL_SENSE = 29, /**< ONEWIRE control register(29) (r/-): Current state of the bus line */
ONEWIRE_CTRL_PRESENCE = 30, /**< ONEWIRE control register(30) (r/-): Bus presence detected */
ONEWIRE_CTRL_BUSY = 31, /**< ONEWIRE control register(31) (r/-): Operation in progress when set */
};
/** ONEWIRE receive/transmit data register bits */
enum NEORV32_ONEWIRE_DATA_enum {
ONEWIRE_DATA_LSB = 0, /**< ONEWIRE data register(0) (r/w): Receive/transmit data (8-bit) LSB */
ONEWIRE_DATA_MSB = 7 /**< ONEWIRE data register(7) (r/w): Receive/transmit data (8-bit) MSB */
};
/**@}*/
// prototypes - setup/management
int neorv32_onewire_available(void);
int neorv32_onewire_setup(uint32_t t_base);

23
sw/lib/include/neorv32_pwm.h
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@ -43,6 +43,29 @@
#ifndef neorv32_pwm_h
#define neorv32_pwm_h
/**********************************************************************//**
* @name IO Device: Pulse Width Modulation Controller (PWM)
**************************************************************************/
/**@{*/
/** PWM module prototype */
typedef volatile struct __attribute__((packed,aligned(4))) {
uint32_t CTRL; /**< offset 0: control register (#NEORV32_PWM_CTRL_enum) */
uint32_t DC[3]; /**< offset 4..12: duty cycle register 0..2 */
} neorv32_pwm_t;
/** PWM module hardware access (#neorv32_pwm_t) */
#define NEORV32_PWM ((neorv32_pwm_t*) (NEORV32_PWM_BASE))
/** PWM control register bits */
enum NEORV32_PWM_CTRL_enum {
PWM_CTRL_EN = 0, /**< PWM control register(0) (r/w): PWM controller enable */
PWM_CTRL_PRSC0 = 1, /**< PWM control register(1) (r/w): Clock prescaler select bit 0 */
PWM_CTRL_PRSC1 = 2, /**< PWM control register(2) (r/w): Clock prescaler select bit 1 */
PWM_CTRL_PRSC2 = 3 /**< PWM control register(3) (r/w): Clock prescaler select bit 2 */
};
/**@}*/
// prototypes
int neorv32_pwm_available(void);
void neorv32_pwm_setup(int prsc);

35
sw/lib/include/neorv32_sdi.h
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@ -43,6 +43,41 @@
#ifndef neorv32_sdi_h
#define neorv32_sdi_h
/**********************************************************************//**
* @name IO Device: Serial Data Interface (SDI)
**************************************************************************/
/**@{*/
/** SDI module prototype */
typedef volatile struct __attribute__((packed,aligned(4))) {
uint32_t CTRL; /**< offset 0: control register (#NEORV32_SDI_CTRL_enum) */
uint32_t DATA; /**< offset 4: data register */
} neorv32_sdi_t;
/** SDI module hardware access (#neorv32_sdi_t) */
#define NEORV32_SDI ((neorv32_sdi_t*) (NEORV32_SDI_BASE))
/** SDI control register bits */
enum NEORV32_SDI_CTRL_enum {
SDI_CTRL_EN = 0, /**< SDI control register(00) (r/w): SID module enable */
SDI_CTRL_CLR_RX = 1, /**< SDI control register(01) (-/w): Clear RX FIFO when set, auto-clear */
SDI_CTRL_FIFO_LSB = 4, /**< SDI control register(04) (r/-): log2 of SDI FIFO size, LSB */
SDI_CTRL_FIFO_MSB = 7, /**< SDI control register(07) (r/-): log2 of SDI FIFO size, MSB */
SDI_CTRL_IRQ_RX_AVAIL = 15, /**< SDI control register(15) (r/w): IRQ when RX FIFO not empty */
SDI_CTRL_IRQ_RX_HALF = 16, /**< SDI control register(16) (r/w): IRQ when RX FIFO at least half full */
SDI_CTRL_IRQ_RX_FULL = 17, /**< SDI control register(17) (r/w): IRQ when RX FIFO full */
SDI_CTRL_IRQ_TX_EMPTY = 18, /**< SDI control register(18) (r/w): IRQ when TX FIFO empty */
SDI_CTRL_RX_AVAIL = 23, /**< SDI control register(23) (r/-): RX FIFO not empty */
SDI_CTRL_RX_HALF = 24, /**< SDI control register(24) (r/-): RX FIFO at least half full */
SDI_CTRL_RX_FULL = 25, /**< SDI control register(25) (r/-): RX FIFO full */
SDI_CTRL_TX_EMPTY = 26, /**< SDI control register(26) (r/-): TX FIFO empty */
SDI_CTRL_TX_FULL = 27 /**< SDI control register(27) (r/-): TX FIFO full */
};
/**@}*/
// prototypes
int neorv32_sdi_available(void);
void neorv32_sdi_setup(uint32_t irq_mask);

47
sw/lib/include/neorv32_spi.h
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@ -43,6 +43,53 @@
#ifndef neorv32_spi_h
#define neorv32_spi_h
/**********************************************************************//**
* @name IO Device: Serial Peripheral Interface Controller (SPI)
**************************************************************************/
/**@{*/
/** SPI module prototype */
typedef volatile struct __attribute__((packed,aligned(4))) {
uint32_t CTRL; /**< offset 0: control register (#NEORV32_SPI_CTRL_enum) */
uint32_t DATA; /**< offset 4: data register */
} neorv32_spi_t;
/** SPI module hardware access (#neorv32_spi_t) */
#define NEORV32_SPI ((neorv32_spi_t*) (NEORV32_SPI_BASE))
/** SPI control register bits */
enum NEORV32_SPI_CTRL_enum {
SPI_CTRL_EN = 0, /**< SPI control register(0) (r/w): SPI unit enable */
SPI_CTRL_CPHA = 1, /**< SPI control register(1) (r/w): Clock phase */
SPI_CTRL_CPOL = 2, /**< SPI control register(2) (r/w): Clock polarity */
SPI_CTRL_CS_SEL0 = 3, /**< SPI control register(3) (r/w): Direct chip select bit 1 */
SPI_CTRL_CS_SEL1 = 4, /**< SPI control register(4) (r/w): Direct chip select bit 2 */
SPI_CTRL_CS_SEL2 = 5, /**< SPI control register(5) (r/w): Direct chip select bit 2 */
SPI_CTRL_CS_EN = 6, /**< SPI control register(6) (r/w): Chip select enable (selected CS line output is low when set) */
SPI_CTRL_PRSC0 = 7, /**< SPI control register(7) (r/w): Clock prescaler select bit 0 */
SPI_CTRL_PRSC1 = 8, /**< SPI control register(8) (r/w): Clock prescaler select bit 1 */
SPI_CTRL_PRSC2 = 9, /**< SPI control register(9) (r/w): Clock prescaler select bit 2 */
SPI_CTRL_CDIV0 = 10, /**< SPI control register(10) (r/w): Clock divider bit 0 */
SPI_CTRL_CDIV1 = 11, /**< SPI control register(11) (r/w): Clock divider bit 1 */
SPI_CTRL_CDIV2 = 12, /**< SPI control register(12) (r/w): Clock divider bit 2 */
SPI_CTRL_CDIV3 = 13, /**< SPI control register(13) (r/w): Clock divider bit 3 */
SPI_CTRL_RX_AVAIL = 16, /**< SPI control register(16) (r/-): RX FIFO data available (RX FIFO not empty) */
SPI_CTRL_TX_EMPTY = 17, /**< SPI control register(17) (r/-): TX FIFO empty */
SPI_CTRL_TX_NHALF = 18, /**< SPI control register(18) (r/-): TX FIFO not at least half full */
SPI_CTRL_TX_FULL = 19, /**< SPI control register(19) (r/-): TX FIFO full */
SPI_CTRL_IRQ_RX_AVAIL = 20, /**< SPI control register(20) (r/w): Fire IRQ if RX FIFO data available (RX FIFO not empty) */
SPI_CTRL_IRQ_TX_EMPTY = 21, /**< SPI control register(21) (r/w): Fire IRQ if TX FIFO empty */
SPI_CTRL_IRQ_TX_HALF = 22, /**< SPI control register(22) (r/w): Fire IRQ if TX FIFO not at least half full */
SPI_CTRL_FIFO_LSB = 23, /**< SPI control register(23) (r/-): log2(FIFO size), lsb */
SPI_CTRL_FIFO_MSB = 26, /**< SPI control register(26) (r/-): log2(FIFO size), msb */
SPI_CTRL_BUSY = 31 /**< SPI control register(31) (r/-): SPI busy flag */
};
/**@}*/
// prototypes
int neorv32_spi_available(void);
void neorv32_spi_setup(int prsc, int cdiv, int clk_phase, int clk_polarity, uint32_t irq_mask);

118
sw/lib/include/neorv32_sysinfo.h Normal file
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@ -0,0 +1,118 @@
// #################################################################################################
// # << NEORV32: neorv32_sysinfo.h - Sys Configuration Information Memory (SYSINFO) HW Driver >> #
// # ********************************************************************************************* #
// # BSD 3-Clause License #
// # #
// # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
// # #
// # Redistribution and use in source and binary forms, with or without modification, are #
// # permitted provided that the following conditions are met: #
// # #
// # 1. Redistributions of source code must retain the above copyright notice, this list of #
// # conditions and the following disclaimer. #
// # #
// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
// # conditions and the following disclaimer in the documentation and/or other materials #
// # provided with the distribution. #
// # #
// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
// # endorse or promote products derived from this software without specific prior written #
// # permission. #
// # #
// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
// # OF THE POSSIBILITY OF SUCH DAMAGE. #
// # ********************************************************************************************* #
// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
// #################################################################################################
/**********************************************************************//**
* @file neorv32_cfs.h
* @brief System Configuration Information Memory (SYSINFO) HW driver header file.
**************************************************************************/
#ifndef neorv32_sysinfo_h
#define neorv32_sysinfo_h
/**********************************************************************//**
* @name IO Device: System Configuration Information Memory (SYSINFO)
**************************************************************************/
/**@{*/
/** SYSINFO module prototype - whole module is read-only */
typedef volatile struct __attribute__((packed,aligned(4))) {
const uint32_t CLK; /**< offset 0: clock speed in Hz */
const uint32_t CUSTOM_ID; /**< offset 4: custom user-defined ID (via top generic) */
const uint32_t SOC; /**< offset 8: SoC features (#NEORV32_SYSINFO_SOC_enum) */
const uint32_t CACHE; /**< offset 12: cache configuration (#NEORV32_SYSINFO_CACHE_enum) */
const uint32_t ISPACE_BASE; /**< offset 16: instruction memory address space base */
const uint32_t DSPACE_BASE; /**< offset 20: data memory address space base */
const uint32_t IMEM_SIZE; /**< offset 24: internal instruction memory (IMEM) size in bytes */
const uint32_t DMEM_SIZE; /**< offset 28: internal data memory (DMEM) size in bytes */
} neorv32_sysinfo_t;
/** SYSINFO module hardware access (#neorv32_sysinfo_t) */
#define NEORV32_SYSINFO ((neorv32_sysinfo_t*) (NEORV32_SYSINFO_BASE))
/** NEORV32_SYSINFO->SOC (r/-): Implemented processor devices/features */
enum NEORV32_SYSINFO_SOC_enum {
SYSINFO_SOC_BOOTLOADER = 0, /**< SYSINFO_FEATURES (0) (r/-): Bootloader implemented when 1 (via INT_BOOTLOADER_EN generic) */
SYSINFO_SOC_MEM_EXT = 1, /**< SYSINFO_FEATURES (1) (r/-): External bus interface implemented when 1 (via MEM_EXT_EN generic) */
SYSINFO_SOC_MEM_INT_IMEM = 2, /**< SYSINFO_FEATURES (2) (r/-): Processor-internal instruction memory implemented when 1 (via MEM_INT_IMEM_EN generic) */
SYSINFO_SOC_MEM_INT_DMEM = 3, /**< SYSINFO_FEATURES (3) (r/-): Processor-internal data memory implemented when 1 (via MEM_INT_DMEM_EN generic) */
SYSINFO_SOC_MEM_EXT_ENDIAN = 4, /**< SYSINFO_FEATURES (4) (r/-): External bus interface uses BIG-endian byte-order when 1 (via MEM_EXT_BIG_ENDIAN generic) */
SYSINFO_SOC_ICACHE = 5, /**< SYSINFO_FEATURES (5) (r/-): Processor-internal instruction cache implemented when 1 (via ICACHE_EN generic) */
SYSINFO_SOC_IS_SIM = 13, /**< SYSINFO_FEATURES (13) (r/-): Set during simulation (not guaranteed) */
SYSINFO_SOC_OCD = 14, /**< SYSINFO_FEATURES (14) (r/-): On-chip debugger implemented when 1 (via ON_CHIP_DEBUGGER_EN generic) */
SYSINFO_SOC_IO_GPIO = 16, /**< SYSINFO_FEATURES (16) (r/-): General purpose input/output port unit implemented when 1 (via IO_GPIO_EN generic) */
SYSINFO_SOC_IO_MTIME = 17, /**< SYSINFO_FEATURES (17) (r/-): Machine system timer implemented when 1 (via IO_MTIME_EN generic) */
SYSINFO_SOC_IO_UART0 = 18, /**< SYSINFO_FEATURES (18) (r/-): Primary universal asynchronous receiver/transmitter 0 implemented when 1 (via IO_UART0_EN generic) */
SYSINFO_SOC_IO_SPI = 19, /**< SYSINFO_FEATURES (19) (r/-): Serial peripheral interface implemented when 1 (via IO_SPI_EN generic) */
SYSINFO_SOC_IO_TWI = 20, /**< SYSINFO_FEATURES (20) (r/-): Two-wire interface implemented when 1 (via IO_TWI_EN generic) */
SYSINFO_SOC_IO_PWM = 21, /**< SYSINFO_FEATURES (21) (r/-): Pulse-width modulation unit implemented when 1 (via IO_PWM_EN generic) */
SYSINFO_SOC_IO_WDT = 22, /**< SYSINFO_FEATURES (22) (r/-): Watchdog timer implemented when 1 (via IO_WDT_EN generic) */
SYSINFO_SOC_IO_CFS = 23, /**< SYSINFO_FEATURES (23) (r/-): Custom functions subsystem implemented when 1 (via IO_CFS_EN generic) */
SYSINFO_SOC_IO_TRNG = 24, /**< SYSINFO_FEATURES (24) (r/-): True random number generator implemented when 1 (via IO_TRNG_EN generic) */
SYSINFO_SOC_IO_SDI = 25, /**< SYSINFO_FEATURES (25) (r/-): Serial data interface implemented when 1 (via IO_SDI_EN generic) */
SYSINFO_SOC_IO_UART1 = 26, /**< SYSINFO_FEATURES (26) (r/-): Secondary universal asynchronous receiver/transmitter 1 implemented when 1 (via IO_UART1_EN generic) */
SYSINFO_SOC_IO_NEOLED = 27, /**< SYSINFO_FEATURES (27) (r/-): NeoPixel-compatible smart LED interface implemented when 1 (via IO_NEOLED_EN generic) */
SYSINFO_SOC_IO_XIRQ = 28, /**< SYSINFO_FEATURES (28) (r/-): External interrupt controller implemented when 1 (via XIRQ_NUM_IO generic) */
SYSINFO_SOC_IO_GPTMR = 29, /**< SYSINFO_FEATURES (29) (r/-): General purpose timer implemented when 1 (via IO_GPTMR_EN generic) */
SYSINFO_SOC_IO_XIP = 30, /**< SYSINFO_FEATURES (30) (r/-): Execute in place module implemented when 1 (via IO_XIP_EN generic) */
SYSINFO_SOC_IO_ONEWIRE = 31 /**< SYSINFO_FEATURES (31) (r/-): 1-wire interface controller implemented when 1 (via IO_ONEWIRE_EN generic) */
};
/** NEORV32_SYSINFO->CACHE (r/-): Cache configuration */
enum NEORV32_SYSINFO_CACHE_enum {
SYSINFO_CACHE_IC_BLOCK_SIZE_0 = 0, /**< SYSINFO_CACHE (0) (r/-): i-cache: log2(Block size in bytes), bit 0 (via ICACHE_BLOCK_SIZE generic) */
SYSINFO_CACHE_IC_BLOCK_SIZE_1 = 1, /**< SYSINFO_CACHE (1) (r/-): i-cache: log2(Block size in bytes), bit 1 (via ICACHE_BLOCK_SIZE generic) */
SYSINFO_CACHE_IC_BLOCK_SIZE_2 = 2, /**< SYSINFO_CACHE (2) (r/-): i-cache: log2(Block size in bytes), bit 2 (via ICACHE_BLOCK_SIZE generic) */
SYSINFO_CACHE_IC_BLOCK_SIZE_3 = 3, /**< SYSINFO_CACHE (3) (r/-): i-cache: log2(Block size in bytes), bit 3 (via ICACHE_BLOCK_SIZE generic) */
SYSINFO_CACHE_IC_NUM_BLOCKS_0 = 4, /**< SYSINFO_CACHE (4) (r/-): i-cache: log2(Number of cache blocks/pages/lines), bit 0 (via ICACHE_NUM_BLOCKS generic) */
SYSINFO_CACHE_IC_NUM_BLOCKS_1 = 5, /**< SYSINFO_CACHE (5) (r/-): i-cache: log2(Number of cache blocks/pages/lines), bit 1 (via ICACHE_NUM_BLOCKS generic) */
SYSINFO_CACHE_IC_NUM_BLOCKS_2 = 6, /**< SYSINFO_CACHE (6) (r/-): i-cache: log2(Number of cache blocks/pages/lines), bit 2 (via ICACHE_NUM_BLOCKS generic) */
SYSINFO_CACHE_IC_NUM_BLOCKS_3 = 7, /**< SYSINFO_CACHE (7) (r/-): i-cache: log2(Number of cache blocks/pages/lines), bit 3 (via ICACHE_NUM_BLOCKS generic) */
SYSINFO_CACHE_IC_ASSOCIATIVITY_0 = 8, /**< SYSINFO_CACHE (8) (r/-): i-cache: log2(associativity), bit 0 (via ICACHE_ASSOCIATIVITY generic) */
SYSINFO_CACHE_IC_ASSOCIATIVITY_1 = 9, /**< SYSINFO_CACHE (9) (r/-): i-cache: log2(associativity), bit 1 (via ICACHE_ASSOCIATIVITY generic) */
SYSINFO_CACHE_IC_ASSOCIATIVITY_2 = 10, /**< SYSINFO_CACHE (10) (r/-): i-cache: log2(associativity), bit 2 (via ICACHE_ASSOCIATIVITY generic) */
SYSINFO_CACHE_IC_ASSOCIATIVITY_3 = 11, /**< SYSINFO_CACHE (11) (r/-): i-cache: log2(associativity), bit 3 (via ICACHE_ASSOCIATIVITY generic) */
SYSINFO_CACHE_IC_REPLACEMENT_0 = 12, /**< SYSINFO_CACHE (12) (r/-): i-cache: replacement policy (0001 = LRU if associativity > 0) bit 0 */
SYSINFO_CACHE_IC_REPLACEMENT_1 = 13, /**< SYSINFO_CACHE (13) (r/-): i-cache: replacement policy (0001 = LRU if associativity > 0) bit 1 */
SYSINFO_CACHE_IC_REPLACEMENT_2 = 14, /**< SYSINFO_CACHE (14) (r/-): i-cache: replacement policy (0001 = LRU if associativity > 0) bit 2 */
SYSINFO_CACHE_IC_REPLACEMENT_3 = 15, /**< SYSINFO_CACHE (15) (r/-): i-cache: replacement policy (0001 = LRU if associativity > 0) bit 3 */
};
/**@}*/
#endif // neorv32_sysinfo_h

25
sw/lib/include/neorv32_trng.h
View file

@ -43,6 +43,31 @@
#ifndef neorv32_trng_h
#define neorv32_trng_h
/**********************************************************************//**
* @name IO Device: True Random Number Generator (TRNG)
**************************************************************************/
/**@{*/
/** TRNG module prototype */
typedef volatile struct __attribute__((packed,aligned(4))) {
uint32_t CTRL; /**< offset 0: control register (#NEORV32_TRNG_CTRL_enum) */
} neorv32_trng_t;
/** TRNG module hardware access (#neorv32_trng_t) */
#define NEORV32_TRNG ((neorv32_trng_t*) (NEORV32_TRNG_BASE))
/** TRNG control/data register bits */
enum NEORV32_TRNG_CTRL_enum {
TRNG_CTRL_DATA_LSB = 0, /**< TRNG data/control register(0) (r/-): Random data byte LSB */
TRNG_CTRL_DATA_MSB = 7, /**< TRNG data/control register(7) (r/-): Random data byte MSB */
TRNG_CTRL_FIFO_CLR = 28, /**< TRNG data/control register(28) (-/w): Clear data FIFO (auto clears) */
TRNG_CTRL_SIM_MODE = 29, /**< TRNG data/control register(29) (r/-): PRNG mode (simulation mode) */
TRNG_CTRL_EN = 30, /**< TRNG data/control register(30) (r/w): TRNG enable */
TRNG_CTRL_VALID = 31 /**< TRNG data/control register(31) (r/-): Random data output valid */
};
/**@}*/
// prototypes
int neorv32_trng_available(void);
void neorv32_trng_enable(void);

41
sw/lib/include/neorv32_twi.h
View file

@ -43,6 +43,47 @@
#ifndef neorv32_twi_h
#define neorv32_twi_h
/**********************************************************************//**
* @name IO Device: Two-Wire Interface Controller (TWI)
**************************************************************************/
/**@{*/
/** TWI module prototype */
typedef volatile struct __attribute__((packed,aligned(4))) {
uint32_t CTRL; /**< offset 0: control register (#NEORV32_TWI_CTRL_enum) */
uint32_t DATA; /**< offset 4: data register (#NEORV32_TWI_DATA_enum) */
} neorv32_twi_t;
/** TWI module hardware access (#neorv32_twi_t) */
#define NEORV32_TWI ((neorv32_twi_t*) (NEORV32_TWI_BASE))
/** TWI control register bits */
enum NEORV32_TWI_CTRL_enum {
TWI_CTRL_EN = 0, /**< TWI control register(0) (r/w): TWI enable */
TWI_CTRL_START = 1, /**< TWI control register(1) (-/w): Generate START condition, auto-clears */
TWI_CTRL_STOP = 2, /**< TWI control register(2) (-/w): Generate STOP condition, auto-clears */
TWI_CTRL_MACK = 3, /**< TWI control register(3) (r/w): Generate ACK by controller for each transmission */
TWI_CTRL_CSEN = 4, /**< TWI control register(4) (r/w): Allow clock stretching when set */
TWI_CTRL_PRSC0 = 5, /**< TWI control register(5) (r/w): Clock prescaler select bit 0 */
TWI_CTRL_PRSC1 = 6, /**< TWI control register(6) (r/w): Clock prescaler select bit 1 */
TWI_CTRL_PRSC2 = 7, /**< TWI control register(7) (r/w): Clock prescaler select bit 2 */
TWI_CTRL_CDIV0 = 8, /**< TWI control register(8) (r/w): Clock divider bit 0 */
TWI_CTRL_CDIV1 = 9, /**< TWI control register(9) (r/w): Clock divider bit 1 */
TWI_CTRL_CDIV2 = 10, /**< TWI control register(10) (r/w): Clock divider bit 2 */
TWI_CTRL_CDIV3 = 11, /**< TWI control register(11) (r/w): Clock divider bit 3 */
TWI_CTRL_CLAIMED = 29, /**< TWI control register(29) (r/-): Set if the TWI bus is currently claimed by any controller */
TWI_CTRL_ACK = 30, /**< TWI control register(30) (r/-): ACK received when set */
TWI_CTRL_BUSY = 31 /**< TWI control register(31) (r/-): Transfer in progress, busy flag */
};
/** TWI receive/transmit data register bits */
enum NEORV32_TWI_DATA_enum {
TWI_DATA_LSB = 0, /**< TWI data register(0) (r/w): Receive/transmit data (8-bit) LSB */
TWI_DATA_MSB = 7 /**< TWI data register(7) (r/w): Receive/transmit data (8-bit) MSB */
};
/**@}*/
// prototypes
int neorv32_twi_available(void);
void neorv32_twi_setup(int prsc, int cdiv, int csen);

54
sw/lib/include/neorv32_uart.h
View file

@ -44,6 +44,60 @@
// Libs required by functions
#include <stdarg.h>
/**********************************************************************//**
* @name IO Device: Primary/Secondary Universal Asynchronous Receiver and Transmitter (UART0 / UART1)
**************************************************************************/
/**@{*/
/** UART module prototype */
typedef volatile struct __attribute__((packed,aligned(4))) {
uint32_t CTRL; /**< offset 0: control register (#NEORV32_UART_CTRL_enum) */
uint32_t DATA; /**< offset 4: data register */
} neorv32_uart_t;
/** UART0 module hardware access (#neorv32_uart_t) */
#define NEORV32_UART0 ((neorv32_uart_t*) (NEORV32_UART0_BASE))
/** UART1 module hardware access (#neorv32_uart_t) */
#define NEORV32_UART1 ((neorv32_uart_t*) (NEORV32_UART1_BASE))
/** UART control register bits */
enum NEORV32_UART_CTRL_enum {
UART_CTRL_EN = 0, /**< UART control register(0) (r/w): UART global enable */
UART_CTRL_SIM_MODE = 1, /**< UART control register(1) (r/w): Simulation output override enable */
UART_CTRL_HWFC_EN = 2, /**< UART control register(2) (r/w): Enable RTS/CTS hardware flow-control */
UART_CTRL_PRSC0 = 3, /**< UART control register(3) (r/w): clock prescaler select bit 0 */
UART_CTRL_PRSC1 = 4, /**< UART control register(4) (r/w): clock prescaler select bit 1 */
UART_CTRL_PRSC2 = 5, /**< UART control register(5) (r/w): clock prescaler select bit 2 */
UART_CTRL_BAUD0 = 6, /**< UART control register(6) (r/w): BAUD rate divisor, bit 0 */
UART_CTRL_BAUD1 = 7, /**< UART control register(7) (r/w): BAUD rate divisor, bit 1 */
UART_CTRL_BAUD2 = 8, /**< UART control register(8) (r/w): BAUD rate divisor, bit 2 */
UART_CTRL_BAUD3 = 9, /**< UART control register(9) (r/w): BAUD rate divisor, bit 3 */
UART_CTRL_BAUD4 = 10, /**< UART control register(10) (r/w): BAUD rate divisor, bit 4 */
UART_CTRL_BAUD5 = 11, /**< UART control register(11) (r/w): BAUD rate divisor, bit 5 */
UART_CTRL_BAUD6 = 12, /**< UART control register(12) (r/w): BAUD rate divisor, bit 6 */
UART_CTRL_BAUD7 = 13, /**< UART control register(13) (r/w): BAUD rate divisor, bit 7 */
UART_CTRL_BAUD8 = 14, /**< UART control register(14) (r/w): BAUD rate divisor, bit 8 */
UART_CTRL_BAUD9 = 15, /**< UART control register(15) (r/w): BAUD rate divisor, bit 9 */
UART_CTRL_RX_NEMPTY = 16, /**< UART control register(16) (r/-): RX FIFO not empty */
UART_CTRL_RX_HALF = 17, /**< UART control register(17) (r/-): RX FIFO at least half-full */
UART_CTRL_RX_FULL = 18, /**< UART control register(18) (r/-): RX FIFO full */
UART_CTRL_TX_EMPTY = 19, /**< UART control register(19) (r/-): TX FIFO empty */
UART_CTRL_TX_NHALF = 20, /**< UART control register(20) (r/-): TX FIFO not at least half-full */
UART_CTRL_TX_FULL = 21, /**< UART control register(21) (r/-): TX FIFO full */
UART_CTRL_IRQ_RX_NEMPTY = 22, /**< UART control register(22) (r/w): Fire IRQ if RX FIFO not empty */
UART_CTRL_IRQ_RX_HALF = 23, /**< UART control register(23) (r/w): Fire IRQ if RX FIFO at least half-full */
UART_CTRL_IRQ_RX_FULL = 24, /**< UART control register(24) (r/w): Fire IRQ if RX FIFO full */
UART_CTRL_IRQ_TX_EMPTY = 25, /**< UART control register(25) (r/w): Fire IRQ if TX FIFO empty */
UART_CTRL_IRQ_TX_NHALF = 26, /**< UART control register(26) (r/w): Fire IRQ if TX FIFO not at least half-full */
UART_CTRL_RX_OVER = 30, /**< UART control register(30) (r/-): RX FIFO overflow */
UART_CTRL_TX_BUSY = 31 /**< UART control register(31) (r/-): Transmitter busy or TX FIFO not empty */
};
/**@}*/
// prototypes for common used UART functions, applicable to UART0 and UART1
int neorv32_uart_available(neorv32_uart_t *UARTx);
void neorv32_uart_setup(neorv32_uart_t *UARTx, uint32_t baudrate, uint32_t irq_mask);

27
sw/lib/include/neorv32_wdt.h
View file

@ -43,6 +43,33 @@
#ifndef neorv32_wdt_h
#define neorv32_wdt_h
/**********************************************************************//**
* @name IO Device: Watchdog Timer (WDT)
**************************************************************************/
/**@{*/
/** WDT module prototype */
typedef volatile struct __attribute__((packed,aligned(4))) {
uint32_t CTRL; /**< offset 0: control register (#NEORV32_WDT_CTRL_enum) */
} neorv32_wdt_t;
/** WDT module hardware access (#neorv32_wdt_t) */
#define NEORV32_WDT ((neorv32_wdt_t*) (NEORV32_WDT_BASE))
/** WDT control register bits */
enum NEORV32_WDT_CTRL_enum {
WDT_CTRL_EN = 0, /**< WDT control register(0) (r/w): Watchdog enable */
WDT_CTRL_LOCK = 1, /**< WDT control register(1) (r/w): Lock write access to control register, clears on reset only */
WDT_CTRL_DBEN = 2, /**< WDT control register(2) (r/w): Allow WDT to continue operation even when CPU is in debug mode */
WDT_CTRL_SEN = 3, /**< WDT control register(3) (r/w): Allow WDT to continue operation even when CPU is in sleep mode */
WDT_CTRL_RESET = 4, /**< WDT control register(4) (-/w): Reset WDT counter when set, auto-clears */
WDT_CTRL_RCAUSE = 5, /**< WDT control register(5) (r/-): Cause of last system reset: 0=external reset, 1=watchdog */
WDT_CTRL_TIMEOUT_LSB = 8, /**< WDT control register(8) (r/w): Timeout value, LSB */
WDT_CTRL_TIMEOUT_MSB = 31 /**< WDT control register(31) (r/w): Timeout value, MSB */
};
/**@}*/
// prototypes
int neorv32_wdt_available(void);
void neorv32_wdt_setup(uint32_t timeout, int lock, int debug_en, int sleep_en);

42
sw/lib/include/neorv32_xip.h
View file

@ -43,6 +43,48 @@
#ifndef neorv32_xip_h
#define neorv32_xip_h
/**********************************************************************//**
* @name IO Device: Execute In Place Module (XIP)
**************************************************************************/
/**@{*/
/** XIP module prototype */
typedef volatile struct __attribute__((packed,aligned(4))) {
uint32_t CTRL; /**< offset 0: control register (#NEORV32_XIP_CTRL_enum) */
const uint32_t reserved; /**< offset 4: reserved */
uint32_t DATA_LO; /**< offset 8: SPI data register low */
uint32_t DATA_HI; /**< offset 12: SPI data register high */
} neorv32_xip_t;
/** XIP module hardware access (#neorv32_xip_t) */
#define NEORV32_XIP ((neorv32_xip_t*) (NEORV32_XIP_BASE))
/** XIP control/data register bits */
enum NEORV32_XIP_CTRL_enum {
XIP_CTRL_EN = 0, /**< XIP control register( 0) (r/w): XIP module enable */
XIP_CTRL_PRSC0 = 1, /**< XIP control register( 1) (r/w): Clock prescaler select bit 0 */
XIP_CTRL_PRSC1 = 2, /**< XIP control register( 2) (r/w): Clock prescaler select bit 1 */
XIP_CTRL_PRSC2 = 3, /**< XIP control register( 3) (r/w): Clock prescaler select bit 2 */
XIP_CTRL_CPOL = 4, /**< XIP control register( 4) (r/w): SPI (idle) clock polarity */
XIP_CTRL_CPHA = 5, /**< XIP control register( 5) (r/w): SPI clock phase */
XIP_CTRL_SPI_NBYTES_LSB = 6, /**< XIP control register( 6) (r/w): Number of bytes in SPI transmission, LSB */
XIP_CTRL_SPI_NBYTES_MSB = 9, /**< XIP control register( 9) (r/w): Number of bytes in SPI transmission, MSB */
XIP_CTRL_XIP_EN = 10, /**< XIP control register(10) (r/w): XIP access enable */
XIP_CTRL_XIP_ABYTES_LSB = 11, /**< XIP control register(11) (r/w): Number XIP address bytes (minus 1), LSB */
XIP_CTRL_XIP_ABYTES_MSB = 12, /**< XIP control register(12) (r/w): Number XIP address bytes (minus 1), MSB */
XIP_CTRL_RD_CMD_LSB = 13, /**< XIP control register(13) (r/w): SPI flash read command, LSB */
XIP_CTRL_RD_CMD_MSB = 20, /**< XIP control register(20) (r/w): SPI flash read command, MSB */
XIP_CTRL_PAGE_LSB = 21, /**< XIP control register(21) (r/w): XIP memory page, LSB */
XIP_CTRL_PAGE_MSB = 24, /**< XIP control register(24) (r/w): XIP memory page, MSB */
XIP_CTRL_SPI_CSEN = 25, /**< XIP control register(25) (r/w): SPI chip-select enable */
XIP_CTRL_HIGHSPEED = 26, /**< XIP control register(26) (r/w): SPI high-speed mode enable (ignoring XIP_CTRL_PRSC) */
XIP_CTRL_BURST_EN = 27, /**< XIP control register(27) (r/w): Enable XIP burst mode */
XIP_CTRL_PHY_BUSY = 30, /**< XIP control register(20) (r/-): SPI PHY is busy */
XIP_CTRL_XIP_BUSY = 31 /**< XIP control register(31) (r/-): XIP access in progress */
};
/**@}*/
// prototypes
int neorv32_xip_available(void);
int neorv32_xip_setup(uint8_t prsc, uint8_t cpol, uint8_t cpha, uint8_t rd_cmd);

17
sw/lib/include/neorv32_xirq.h
View file

@ -41,6 +41,23 @@
#ifndef neorv32_xirq_h
#define neorv32_xirq_h
/**********************************************************************//**
* @name IO Device: External Interrupt Controller (XIRQ)
**************************************************************************/
/**@{*/
/** XIRQ module prototype */
typedef volatile struct __attribute__((packed,aligned(4))) {
uint32_t IER; /**< offset 0: IRQ input enable register */
uint32_t IPR; /**< offset 4: pending IRQ register /ack/clear */
uint32_t SCR; /**< offset 8: interrupt source register */
const uint32_t reserved; /**< offset 12: reserved */
} neorv32_xirq_t;
/** XIRQ module hardware access (#neorv32_xirq_t) */
#define NEORV32_XIRQ ((neorv32_xirq_t*) (NEORV32_XIRQ_BASE))
/**@}*/
// prototypes
int neorv32_xirq_available(void);
int neorv32_xirq_setup(void);