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[docs] use inline wavedrom
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stnolting
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6 changed files with 155 additions and 15 deletions
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@ -459,7 +459,34 @@ The figure below shows three exemplary bus accesses:
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. A failing read access to address `C_addr` (slow response; `ERR` arrives after several cycles).
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.Three Exemplary Bus Transactions (showing only in-band signals; privileged non-debug non-atomic accesses)
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image::bus_interface.png[700]
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[wavedrom, format="svg", align="center"]
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----
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{signal: [
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{name: 'clk', wave: 'p..|.......|..'},
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[
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"request",
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{name: 'addr', wave: 'x3.|.x4.x5.|.x', data: ['A_addr', 'B_addr', 'C_addr']},
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{name: 'data', wave: 'x..|..4.x..|..', data: ['wdata']},
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{name: 'ben', wave: 'x..|..4.x..|..', data: ['ben']},
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{name: 'stb', wave: '010|..10.10|..', node: '.a....d..f....'},
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{name: 'rw', wave: 'x0.|.x1.x0.|..', node: '..............'},
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{name: 'src', wave: 'x0.|.x0.x0.|.x'},
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{name: 'priv', wave: 'x1.|.x1.x1.|.x'},
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{name: 'debug', wave: 'x0.|.x0.x0.|.x'},
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{name: 'amo', wave: 'x0.|.x0.x0.|.x'},
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{name: 'amoop', wave: 'x0.|.x0.x0.|.x'},
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],
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{},
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[
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"response",
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{name: 'data', wave: '2..|32.....|x2', data: ['0', 'rdata', '0'], node: '....b.......g.'},
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{name: 'ack', wave: '0..|10.10..|..', node: '....c..e......'},
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{name: 'err', wave: '0..|.......|10', node: '............h.'}
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]
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],
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edge: ['a~>b', 'a~>c', 'd~>e', 'f~>g', 'f~>h']
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}
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----
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.Adding Register Stages
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[TIP]
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@ -65,7 +65,16 @@ value. The actual data bits are transferred by modifying the duty cycle of the s
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WS2812 are shown below). A RESET command is "send" by pulling the data line LOW for at least 50μs.
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.WS2812 bit-level timing (timing does not scale)
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image::neopixel_timing.png[align=left]
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[wavedrom, format="svg", align="center"]
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----
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{signal: [
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{name: '0-code', wave: '01...0...1', node: '.a...b...c' },
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{name: '1-code', wave: '01....0..1', node: '.d....e..f' },
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{name: 'reset', wave: '10.......1', node: '.g.......h' },
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],
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edge: ['a~>b T0H', 'b~>c T0L', 'd~>e T1H', 'e~>f T1L', 'g~>h TRESET']
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}
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----
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.WS2812 interface timing
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[cols="<2,<2,<6"]
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@ -118,13 +118,41 @@ controller: single-bit (0 or 1) transaction and reset with presence detect. Note
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the single-bit operation eight times. The relevant points in time are shown as _absolute_ time points (in multiples of the
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time base T~base~) with the falling edge of the bus as reference points.
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[cols="^2,^2"]
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[grid="none"]
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|=======================
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a| image::onewire_data.png[align=center]
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a| image::onewire_reset.png[align=center]
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| Single-bit data transmission (not to scale) | Reset pulse and presence detect (not to scale)
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|=======================
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.Single-bit data transmission (not to scale)
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[wavedrom, format="svg", align="center"]
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----
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{ signal: [
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{ wave: '10x....1.', node: '.........'},
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{ node: '.ab......'},
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{ node: '.X..c....'},
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{ node: '.Y.....d.'},
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{ node: '.Z......e'}
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],
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edge: [
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'a-b t0',
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'X-c t1',
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'Y-d t2',
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'Z-e t3'
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]
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}
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----
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.Reset pulse and presence detect (not to scale)
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[wavedrom, format="svg", align="center"]
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----
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{ signal: [
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{ wave: '10..x...1', node: '.........'},
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{ node: '.f..g....'},
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{ node: '.X.. h...'},
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{ node: '.Y......i'}
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],
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edge: [
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'f-g t4',
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'X-h t5',
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'Y-i t6',
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]
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}
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----
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.Data Transmission Timing
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[cols="<2,<6,^3,^3"]
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@ -49,6 +49,18 @@ The SLINK interface consists of four signals for each channel:
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* `rdy` indicates that the receiver is ready to receive
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* `src` and `dst` provide source/destination routing information (optional)
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.SLINK example transmissions
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[wavedrom, format="svg", align="center"]
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----
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{signal: [
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{name: 'clk', wave: 'p.........'},
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{name: 'dat', wave: 'x345..6x7x', data: ["A", "B", "C", "D", "E"]},
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{name: 'val', wave: '01.....010'},
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{name: 'rdy', wave: '01.0.1...0'},
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{name: 'lst', wave: '0.......10'},
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]}
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----
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.AXI4-Stream Compatibility
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[NOTE]
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The interface names (except for `src` and `dst`) and the underlying protocol is compatible to the AXI4-Stream protocol standard.
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@ -91,7 +91,43 @@ two operation types are illustrated in the following figure (note that the trans
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to improve readability).
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.TWD single-byte read and write transaction timing (not to scale)
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image::twd_sequences.png[]
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[wavedrom, format="svg", align="center"]
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----
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{signal: [
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[
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"write byte",
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{name: 'SDA', wave: '10.7..7..7..7..7..7..7..0..0..x|.', node: 'a.b.....................c..d..e', data: ['A6', 'A5', 'A4', 'A3', 'A2', 'A1', 'A0']},
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{name: 'SCL', wave: '1.0.10.10.10.10.10.10.10.10.10.|.'},
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{},
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{name: 'SDA', wave: 'x|.5..5..5..5..5..5..5..5..0..0.1', node: '...........................f..gh.i', data: ['D7', 'D6', 'D5', 'D4', 'D3', 'D2', 'D1', 'D0']},
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{name: 'SCL', wave: '0|..10.10.10.10.10.10.10.10.10.1.'}
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],
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{},
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{},
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[
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"read byte",
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{name: 'SDA', wave: '10.7..7..7..7..7..7..7..1..0..x|.', node: 'j.k.....................l..m..n', data: ['A6', 'A5', 'A4', 'A3', 'A2', 'A1', 'A0']},
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{name: 'SCL', wave: '1.0.10.10.10.10.10.10.10.10.10.|.'},
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{},
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{name: 'SDA', wave: 'x|.9..9..9..9..9..9..9..9..0..0.1', node: '...........................o..pq.r', data: ['D7', 'D6', 'D5', 'D4', 'D3', 'D2', 'D1', 'D0']},
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{name: 'SCL', wave: '0|..10.10.10.10.10.10.10.10.10.1.'}
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]
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],
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edge: [
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'a-b START',
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'c-d WRITE',
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'd-e ACK by TWD',
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'f-g ACK by TWD',
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'h-i STOP',
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'j-k START',
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'l-m READ',
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'm-n ACK by TWD',
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'o-p ACK by HOST',
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'q-r STOP'
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]
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}
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----
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Any new transaction starts with a **START** condition. Then, the host transmits the 7 bit device address MSB-first
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(green signals `A6` to `A0`) plus a command bit. The command bit can be either **write** (pulling the SDA line low)
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@ -56,17 +56,45 @@ do not allow any bus timeouts. Hence, `XBUS_TIMEOUT` should be set to zero (disa
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when using the XBUS-AHB bridge.
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**Wishbone Bus Protocol**
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**XBUS Bus Protocol**
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The external bus interface complies to the **pipelined Wishbone b4** protocol. Even though this protocol
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was explicitly designed to support pipelined transfers, only a single transfer will be "in fly" at once.
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Hence, just two types of bus transactions are generated by the XBUS controller (see images below).
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.XBUS/Wishbone Write Transaction
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image::xbus_write.png[700]
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.XBUS Write Transaction
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[wavedrom, format="svg", align="center"]
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----
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{signal: [
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{name: 'clk', wave: 'p....|...'},
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{name: 'xbus_adr_o', wave: 'x3...|.x.', data: ['address']},
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{name: 'xbus_dat_i', wave: 'x....|.x.'},
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{name: 'xbus_dat_o', wave: 'x3...|.x.', data: ['wdata']},
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{name: 'xbus_we_o', wave: 'x1...|.x.'},
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{name: 'xbus_sel_o', wave: 'x3...|.x.', data: ['byte_enable']},
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{name: 'xbus_stb_o', wave: '010..|...'},
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{name: 'xbus_cyc_o', wave: '01...|.0.'},
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{name: 'xbus_ack_i', wave: 'x0...|1x.'},
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{name: 'xbus_err_i', wave: 'x0...|.x.'},
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]}
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----
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.XBUS/Wishbone Read Transaction
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image::xbus_read.png[700]
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.XBUS Read Transaction
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[wavedrom, format="svg", align="center"]
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----
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{signal: [
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{name: 'clk', wave: 'p....|...'},
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{name: 'xbus_adr_o', wave: 'x3...|.x.', data: ['address']},
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{name: 'xbus_dat_i', wave: 'x....|3x.', data: ['rdata']},
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{name: 'xbus_dat_o', wave: 'x....|.x.'},
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{name: 'xbus_we_o', wave: 'x0...|.x.'},
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{name: 'xbus_sel_o', wave: 'x....|.x.'},
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{name: 'xbus_stb_o', wave: '010..|...'},
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{name: 'xbus_cyc_o', wave: '01...|.0.'},
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{name: 'xbus_ack_i', wave: 'x0...|1x.'},
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{name: 'xbus_err_i', wave: 'x0...|.x.'},
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]}
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----
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.Wishbone "Classic" Protocol
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[IMPORTANT]
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