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rtl: processor_templates: enable Zicntr ISA extension on minimal templates

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Re-enable the Zicntr ISA extension on the neorv32_ProcessorTop_Minimal
and neorv32_ProcessorTop_MinimalBoot templates to restore RISC-V
compliance.

This allows for an easier path for evaluating 3rd party software
depending on Zicntr (e.g. the Zephyr RTOS).

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
This commit is contained in:
Henrik Brix Andersen 2025-03-04 21:11:40 +00:00
parent 5753b32bd4
commit 24ff7c64be
2 changed files with 4 additions and 0 deletions
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2
rtl/processor_templates/neorv32_ProcessorTop_Minimal.vhd
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@ -51,6 +51,8 @@ begin
CLOCK_FREQUENCY => CLOCK_FREQUENCY, -- clock frequency of clk_i in Hz
-- Boot Configuration --
BOOT_MODE_SELECT => 2, -- boot from pre-initialized interal IMEM
-- RISC-V CPU Extensions --
RISCV_ISA_Zicntr => true, -- implement base counters?
-- Internal Instruction memory --
MEM_INT_IMEM_EN => MEM_INT_IMEM_EN, -- implement processor-internal instruction memory
MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes

2
rtl/processor_templates/neorv32_ProcessorTop_MinimalBoot.vhd
View file

@ -57,6 +57,8 @@ begin
CLOCK_FREQUENCY => CLOCK_FREQUENCY, -- clock frequency of clk_i in Hz
-- Boot Configuration --
BOOT_MODE_SELECT => 0, -- boot via internal bootloader
-- RISC-V CPU Extensions --
RISCV_ISA_Zicntr => true, -- implement base counters?
-- Internal Instruction memory --
MEM_INT_IMEM_EN => MEM_INT_IMEM_EN, -- implement processor-internal instruction memory
MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes