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[docs] cleanup rtl file overview
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stnolting
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1 changed files with 80 additions and 79 deletions
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@ -130,36 +130,36 @@ The root directory of the repository is considered the NEORV32 base or home fold
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.Folder Structure
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...................................
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neorv32 - Project home folder
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neorv32 - Project home folder
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│
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├docs - Project documentation
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│├datasheet - AsciiDoc sources for the NEORV32 data sheet
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│├figures - Figures and logos
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│├references - Data sheets and RISC-V specs
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│├sources - Sources for the images in 'figures/'
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│└userguide - AsciiDoc sources for the NEORV32 user guide
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├-docs - Project documentation
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│ ├-datasheet - AsciiDoc sources for the NEORV32 data sheet
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│ ├-figures - Figures and logos
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│ ├-references - Data sheets and RISC-V specs
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│ ├-sources - Sources for the images in 'figures/'
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│ └-userguide - AsciiDoc sources for the NEORV32 user guide
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│
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├rtl - VHDL sources
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│├core - Core sources of the CPU & SoC
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│├processor_templates - Pre-configured SoC wrappers
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│├system_integration - System wrappers and bridges for advanced connectivity
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│└test_setups - Minimal test setup "SoCs" used in the User Guide
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├-rtl - VHDL sources
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│ ├-core - Core sources of the CPU & SoC
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│ ├-processor_templates - Pre-configured SoC wrappers
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│ ├-system_integration - System wrappers and bridges for advanced connectivity
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│ └-test_setups - Minimal test setup "SoCs" used in the User Guide
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│
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├sim - Simulation files
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├-sim - Simulation files
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│
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└-sw - Software framework
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├bootloader - Sources of the processor-internal bootloader
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├common - Linker script, crt0.S start-up code and central makefile
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├example - Example programs for the core and the SoC modules
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│├eclipse - Pre-configured Eclipse IDE project
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│└... - Several example programs
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├lib - Processor core library
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│├include - NEORV32 core library header files (*.h)
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│└source - NEORV32 core library source files (*.c)
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├image_gen - Helper program to generate executables & memory images
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├ocd_firmware - Firmware for the on-chip debugger's "park loop"
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├openocd - OpenOCD configuration files
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└svd - Processor system view description file (CMSIS-SVD)
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└-sw - Software framework
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├-bootloader - Sources of the processor-internal bootloader
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├-common - Linker script, crt0.S start-up code and central makefile
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├-example - Example programs for the core and the SoC modules
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│ ├-eclipse - Pre-configured Eclipse IDE project
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│ └-... - Several example programs
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├-lib - Processor core library
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│ ├-include - NEORV32 core library header files (*.h)
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│ └-source - NEORV32 core library source files (*.c)
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├-image_gen - Helper program to generate executables & memory images
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├-ocd_firmware - Firmware for the on-chip debugger's "park loop"
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├-openocd - OpenOCD configuration files
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└-svd - Processor system view description file (CMSIS-SVD)
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...................................
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@ -179,60 +179,61 @@ All core VHDL files from the list below have to be assigned to a **new library**
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[NOTE]
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See section <<_file_list_files>> for more information.
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.RTL File List and Hierarchy (in alphabetical order)
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.RTL File List (in alphabetical order)
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...................................
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neorv32_top.vhd - NEORV32 PROCESSOR/SOC TOP ENTITY
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│
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├neorv32_cpu.vhd - NEORV32 CPU TOP ENTITY
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│├neorv32_cpu_alu.vhd - Arithmetic/logic unit
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││├neorv32_cpu_cp_bitmanip.vhd - Bit-manipulation co-processor (B ext.)
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││├neorv32_cpu_cp_cfu.vhd - Custom instructions co-processor (Zxcfu ext.)
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││├neorv32_cpu_cp_cond.vhd - Integer conditional co-processor (Zicond ext.)
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││├neorv32_cpu_cp_crypto.vhd - Scalar cryptographic co-processor (Zk*/Zbk* ext.)
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││├neorv32_cpu_cp_fpu.vhd - Floating-point co-processor (Zfinx ext.)
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││├neorv32_cpu_cp_muldiv.vhd - Mul/Div co-processor (M ext.)
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││└neorv32_cpu_cp_shifter.vhd - Bit-shift co-processor (base ISA)
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│├neorv32_cpu_control.vhd - CPU control, exception system and CSRs
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││└neorv32_cpu_decompressor.vhd - Compressed instructions decoder (C ext.)
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│├neorv32_cpu_icc.vhd - Inter-core communication unit
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│├neorv32_cpu_lsu.vhd - Load/store unit
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│├neorv32_cpu_pmp.vhd - Physical memory protection unit (Smpmp ext.)
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│└neorv32_cpu_regfile.vhd - Data register file
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│
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├neorv32_boot_rom.vhd - Bootloader ROM
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│└neorv32_bootloader_image.vhd - Bootloader ROM memory image (package)
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├neorv32_bus.vhd - SoC bus infrastructure modules
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├neorv32_cache.vhd - Generic cache module
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├neorv32_cfs.vhd - Custom functions subsystem
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├neorv32_clint.vhd - Core local interruptor
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├neorv32_clockgate.vhd - Generic clock gating switch
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├neorv32_crc.vhd - Cyclic redundancy check unit
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├neorv32_debug_dm.vhd - on-chip debugger: debug module
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├neorv32_debug_auth.vhd - on-chip debugger: authentication module
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├neorv32_debug_dtm.vhd - on-chip debugger: debug transfer module
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├neorv32_dma.vhd - Direct memory access controller
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├neorv32_dmem.vhd - Generic processor-internal data memory
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├neorv32_fifo.vhd - Generic FIFO component
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├neorv32_gpio.vhd - General purpose input/output port unit
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├neorv32_gptmr.vhd - General purpose 32-bit timer
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├neorv32_imem.vhd - Generic processor-internal instruction memory
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│└neorv32_application_image.vhd - IMEM application initialization image (package)
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├neorv32_neoled.vhd - NeoPixel (TM) compatible smart LED interface
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├neorv32_onewire.vhd - One-Wire serial interface controller
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├neorv32_package.vhd - Main VHDL package file
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├neorv32_pwm.vhd - Pulse-width modulation controller
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├neorv32_sdi.vhd - Serial data interface controller (SPI device)
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├neorv32_slink.vhd - Stream link interface
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├neorv32_spi.vhd - Serial peripheral interface controller (SPI host)
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├neorv32_sys.vhd - System infrastructure modules
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├neorv32_sysinfo.vhd - System configuration information memory
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├neorv32_trng.vhd - True random number generator
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├neorv32_twi.vhd - Two wire serial interface controller
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├neorv32_uart.vhd - Universal async. receiver/transmitter
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├neorv32_wdt.vhd - Watchdog timer
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├neorv32_xbus.vhd - External (Wishbone) bus interface gateways
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├neorv32_xip.vhd - Execute in place module
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└neorv32_xirq.vhd - External interrupt controller
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rtl/core
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├-neorv32_application_image.vhd - IMEM application initialization image (package)
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├-neorv32_boot_rom.vhd - Bootloader ROM
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├-neorv32_bootloader_image.vhd - Bootloader ROM memory image (package)
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├-neorv32_bus.vhd - SoC bus infrastructure modules
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├-neorv32_cache.vhd - Generic cache module
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├-neorv32_clint.vhd - Core local interruptor
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├-neorv32_clockgate.vhd - Generic clock gating switch
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├-neorv32_cfs.vhd - Custom functions subsystem
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├-neorv32_core_complex.vhd - NEORV32 CORE COMPLEX TOP ENTITY
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├-neorv32_cpu.vhd - NEORV32 CPU TOP ENTITY
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├-neorv32_cpu_alu.vhd - Arithmetic/logic unit
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├-neorv32_cpu_control.vhd - CPU control, exception system and CSRs
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├-neorv32_cpu_cp_bitmanip.vhd - Bit-manipulation co-processor (B ext.)
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├-neorv32_cpu_cp_cfu.vhd - Custom instructions co-processor (Zxcfu ext.)
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├-neorv32_cpu_cp_cond.vhd - Integer conditional co-processor (Zicond ext.)
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├-neorv32_cpu_cp_crypto.vhd - Scalar cryptography co-processor (Zk*/Zbk* ext.)
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├-neorv32_cpu_cp_fpu.vhd - Floating-point co-processor (Zfinx ext.)
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├-neorv32_cpu_cp_muldiv.vhd - Mul/Div co-processor (M ext.)
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├-neorv32_cpu_cp_shifter.vhd - Bit-shift co-processor (base ISA)
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├-neorv32_cpu_decompressor.vhd - Compressed instructions decoder (C ext.)
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├-neorv32_cpu_icc.vhd - Inter-core communication unit
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├-neorv32_cpu_lsu.vhd - Load/store unit
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├-neorv32_cpu_pmp.vhd - Physical memory protection unit (Smpmp ext.)
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├-neorv32_cpu_regfile.vhd - Data register file
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├-neorv32_crc.vhd - Cyclic redundancy check unit
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├-neorv32_debug_auth.vhd - On-chip debugger: authentication module
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├-neorv32_debug_dm.vhd - On-chip debugger: debug module
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├-neorv32_debug_dtm.vhd - On-chip debugger: debug transfer module
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├-neorv32_dma.vhd - Direct memory access controller
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├-neorv32_dmem.vhd - Generic processor-internal data memory
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├-neorv32_fifo.vhd - Generic FIFO component
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├-neorv32_gpio.vhd - General purpose input/output port unit
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├-neorv32_gptmr.vhd - General purpose 32-bit timer
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├-neorv32_imem.vhd - Generic processor-internal instruction memory
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├-neorv32_neoled.vhd - NeoPixel (TM) compatible smart LED interface
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├-neorv32_onewire.vhd - One-Wire serial interface controller
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├-neorv32_package.vhd - Main VHDL package file
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├-neorv32_pwm.vhd - Pulse-width modulation controller
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├-neorv32_sdi.vhd - Serial data interface controller (SPI device)
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├-neorv32_slink.vhd - Stream link interface
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├-neorv32_spi.vhd - Serial peripheral interface controller (SPI host)
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├-neorv32_sys.vhd - System infrastructure modules
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├-neorv32_sysinfo.vhd - System configuration information memory
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├-neorv32_top.vhd - NEORV32 PROCESSOR/SOC TOP ENTITY
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├-neorv32_trng.vhd - True random number generator
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├-neorv32_twd.vhd - Two wire serial device controller
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├-neorv32_twi.vhd - Two wire serial interface controller
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├-neorv32_uart.vhd - Universal async. receiver/transmitter
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├-neorv32_wdt.vhd - Watchdog timer
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├-neorv32_xbus.vhd - External (Wishbone) bus interface gateways
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├-neorv32_xip.vhd - Execute in place module
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└-neorv32_xirq.vhd - External interrupt controller
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...................................
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.Replacing Modules for Customization or Optimization
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