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fix litex boot

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Pepijn de Vos 2025-03-17 14:22:53 +01:00
parent fc5bc029e5
commit 25b0774967
1 changed files with 5 additions and 1 deletions
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6
rtl/system_integration/neorv32_litex_core_complex.vhd
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@ -78,6 +78,7 @@ architecture neorv32_litex_core_complex_rtl of neorv32_litex_core_complex is
riscv_m : bool_t;
riscv_u : bool_t;
riscv_a : bool_t;
dmem : bool_t;
riscv_zicntr : bool_t;
riscv_zihpm : bool_t;
fast_ops : bool_t;
@ -96,9 +97,10 @@ architecture neorv32_litex_core_complex_rtl of neorv32_litex_core_complex is
riscv_m => ( false, true, true, true, false ), -- RISC-V hardware mul/div 'M'
riscv_u => ( false, false, true, true, false ), -- RISC-V user mode 'U'
riscv_a => ( false, false, false, false, true ), -- RISC-V atomics
dmem => ( false, false, false, false, true ), -- enable data memory
riscv_zicntr => ( false, false, true, true, true ), -- RISC-V standard CPU counters 'Zicntr'
riscv_zihpm => ( false, false, false, true, true ), -- RISC-V hardware performance monitors 'Zihpm'
fast_ops => ( false, false, true, true, true ), -- use DSPs and barrel-shifters
fast_ops => ( false, false, true, true, false ), -- use DSPs and barrel-shifters
pmp_num => ( 0, 0, 0, 8, 0 ), -- number of PMP regions (0..16)
hpm_num => ( 0, 0, 0, 8, 0 ), -- number of HPM counters (0..29)
xcache_en => ( false, false, true, true, false ), -- external bus cache enabled
@ -119,6 +121,7 @@ begin
-- General --
CLOCK_FREQUENCY => 0, -- clock frequency of clk_i in Hz [not required by the core complex]
HART_BASE => HART_ID,
BOOT_MODE_SELECT => 1,
-- On-Chip Debugger (OCD) --
OCD_EN => DEBUG, -- implement on-chip debugger
-- RISC-V CPU Extensions --
@ -132,6 +135,7 @@ begin
-- Tuning Options --
CPU_FAST_MUL_EN => configs_c.fast_ops(CONFIG), -- use DSPs for M extension's multiplier
CPU_FAST_SHIFT_EN => configs_c.fast_ops(CONFIG), -- use barrel shifter for shift operations
MEM_INT_DMEM_EN => configs_c.dmem(CONFIG),
-- Physical Memory Protection (PMP) --
PMP_NUM_REGIONS => configs_c.pmp_num(CONFIG), -- number of regions (0..16)
PMP_MIN_GRANULARITY => 4, -- minimal region granularity in bytes, has to be a power of 2, min 4 bytes