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[docs] add Segger Embedded Studio section

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stnolting 2022-06-13 19:34:34 +02:00
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docs/legal.adoc
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@ -57,6 +57,7 @@ Contact: stnolting@gmail.com
* Images/figures made with _Microsoft Power Point_.
* Timing diagrams made with _WaveDrom Editor_.
* Documentation proudly made with `asciidoctor`.
* "Segger Embedded Studio" and "J-Link" are trademarks of Segger Microcontroller Systems GmbH.
* All further/unreferenced products belong to their according copyright holders.
PDF icons from https://www.flaticon.com and made by

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docs/userguide/debugging_with_ocd.adoc
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@ -16,6 +16,9 @@ The on-chip debugger is only implemented if the _ON_CHIP_DEBUGGER_EN_ generic is
the `Zicsr` and `Zifencei` CPU extension to be implemented (top generics _CPU_EXTENSION_RISCV_Zicsr_ = _true_
and _CPU_EXTENSION_RISCV_Zifencei_ = _true_).
[TIP]
<<_segger_embedded_studio>> can also be used to develop and debug applications for the NEORV32 using the on-chip debugger.
:sectnums:
=== Hardware Requirements
@ -277,3 +280,14 @@ Breakpoint 1 at 0x690
[NOTE]
The CPU's trigger module only provides a single _instruction address match_ type trigger. Hence, only
a single `hb` hardware-assisted breakpoint can be used.
:sectnums:
=== Segger Embedded Studio
Software for the NEORV32 processor can also be developed and debugged _in-system_ using Segger Embedded Studio
and a Segger J-Link probe. The following links provide further information as well as an excellent tutorial.
* Segger Embedded Studio: https://www.segger.com/products/development-tools/embedded-studio
* Segger notes regarding NEORV32: https://wiki.segger.com/J-Link_NEORV32
* Excellent tutorial: https://www.emb4fun.com/riscv/ses4rv/index.html