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[ocd-firmware] update park loop code
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stnolting
parent
d0e04fcd29
commit
2737b3825d
2 changed files with 61 additions and 41 deletions
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@ -1,8 +1,7 @@
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/* ================================================================================ */
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/* NEORV32 CPU - RISC-V GCC Linker Script */
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/* -------------------------------------------------------------------------------- */
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/* For the execution-based on-chip debugger (OCD) code memory ROM: "park loop" code */
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/* (build-in firmware) */
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/* "Park loop" code for execution-based on-chip debugger'S (OCD) code ROM. */
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/* -------------------------------------------------------------------------------- */
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/* The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 */
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/* Copyright (c) NEORV32 contributors. */
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@ -13,11 +12,11 @@
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OUTPUT_FORMAT("elf32-littleriscv")
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OUTPUT_ARCH(riscv)
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ENTRY(__start)
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ENTRY(_ocd_start)
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MEMORY
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{
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debug_mem (rx) : ORIGIN = 0xFFFFFF00, LENGTH = 128
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debug_rom (rx) : ORIGIN = 0xFFFFFE00, LENGTH = 128
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}
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SECTIONS
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@ -25,5 +24,5 @@ SECTIONS
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.text :
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{
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KEEP(*(.text.ocd));
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} > debug_mem
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} > debug_rom
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}
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@ -1,6 +1,8 @@
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// ================================================================================ //
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// NEORV32 CPU - park_loop.S - Execution-Based On-Chip Debugger (OCD) Firmware //
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// -------------------------------------------------------------------------------- //
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// WARNING! This code only supports up to 4 harts! //
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// -------------------------------------------------------------------------------- //
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// The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 //
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// Copyright (c) NEORV32 contributors. //
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// Copyright (c) 2020 - 2024 Stephan Nolting. All rights reserved. //
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@ -8,60 +10,79 @@
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// SPDX-License-Identifier: BSD-3-Clause //
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// ================================================================================ //
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// debug module (DM) address map
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.equ DM_CODE_BASE, 0xffffff00 // base address of debug_module's code ROM (park loop)
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.equ DM_PBUF_BASE, 0xffffff40 // base address of debug_module's program buffer (PBUF)
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.equ DM_DATA_BASE, 0xffffff80 // base address of debug_module's abstract data buffer (DATA)
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.equ DM_SREG_BASE, 0xffffffC0 // base address of debug_module's status register
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// status register (SREG) byte(!) offsets
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.equ SREG_HLT_ACK, ( 0 / 8) // -/w: CPU has halted in debug mode and is waiting in park loop
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.equ SREG_RES_REQ, ( 8 / 8) // r/-: DM requests to resume
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.equ SREG_RES_ACK, ( 8 / 8) // -/w: CPU starts to resume
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.equ SREG_EXE_REQ, (16 / 8) // r/-: DM requests to execute program buffer
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.equ SREG_EXE_ACK, (16 / 8) // -/w: CPU starts to execute program buffer
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.equ SREG_EXC_ACK, (24 / 8) // -/w: CPU has detected an exception while in debug-mode
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.file "park_loop.S"
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.section .text.ocd
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.balign 4
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.option norvc
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.global __start
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.global _ocd_start
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.global entry_exception
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.global entry_normal
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__start:
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// debug module (DM) address map
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.equ DM_CODE_BASE, 0xFFFFFE00 // base address of code ROM (park loop)
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.equ DM_PBUF_BASE, 0xFFFFFE80 // base address of program buffer
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.equ DM_DATA_BASE, 0xFFFFFF00 // base address of abstract data buffer
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.equ DM_SREG_BASE, 0xFFFFFF80 // base address of status register(s)
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// BASE + 0: exception entry - signal EXCEPTION condition to DM and restart parking loop
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// Request register (DM_SREG_BASE read-access) byte-field bits
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.equ REQ_RES, 0 // r/-: DM requests to resume
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.equ REQ_EXE, 1 // r/-: DM requests to execute program buffer
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// Acknowledge register (DM_SREG_BASE write-access) address offsets
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.equ ACK_HLT, 0x0 // -/w: CPU has halted in debug mode and is waiting in park loop
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.equ ACK_RES, 0x4 // -/w: CPU starts to resume
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.equ ACK_EXE, 0x8 // -/w: CPU starts to execute program buffer
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.equ ACK_EXC, 0xC // -/w: CPU has detected an exception while in debug-mode
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_ocd_start:
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// BASE + 0: exception entry - exeption during program buffer execution
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entry_exception:
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sb zero, (DM_SREG_BASE+SREG_EXC_ACK)(zero) // trigger exception-acknowledge to inform DM
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ebreak // re-enter debug mode (at "entry_normal" entry point)
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sw zero, (DM_SREG_BASE+ACK_EXC)(zero) // send exception-acknowledge (no need for a hart ID)
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csrr x8, dscratch0 // restore x8 from dscratch0 (might be changed during PBUF execution)
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ebreak // re-enter debug mode (at "entry_normal" entry point)
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nop
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// BASE + 8: normal entry - ebreak in debug-mode, halt request or return from single-stepped instruction
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// BASE + 16: normal entry - ebreak in debug-mode, halt request or return from single-stepped instruction
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entry_normal:
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csrw dscratch0, x8 // backup x8 to dscratch0 so we have a GPR available
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csrw dscratch0, x8 // backup x8 to dscratch0 so we have a GPR available
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csrr x8, mhartid // get hart ID (0..3)
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sw x8, (DM_SREG_BASE+ACK_HLT)(zero) // send halt-acknowledge
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// polling loop - waiting for requests
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park_loop:
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sb zero, (DM_SREG_BASE+SREG_HLT_ACK)(zero) // ACK that CPU is halted
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lbu x8, (DM_SREG_BASE+SREG_EXE_REQ)(zero) // request to execute program buffer?
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bnez x8, execute
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lbu x8, (DM_SREG_BASE+SREG_RES_REQ)(zero) // request to resume?
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beqz x8, park_loop
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csrr x8, mhartid // get hart ID (0..3)
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lbu x8, DM_SREG_BASE(x8) // read hart-specific byte from request register
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andi x8, x8, 1 << REQ_EXE // execute-request bit set?
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bnez x8, execute
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csrr x8, mhartid // get hart ID (0..3)
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lbu x8, DM_SREG_BASE(x8) // read hart-specific byte from request register
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andi x8, x8, 1 << REQ_RES // resume-request bit set?
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beqz x8, park_loop
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// resume normal operation
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resume:
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sb zero, (DM_SREG_BASE+SREG_RES_ACK)(zero) // ACK that CPU is about to resume
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csrr x8, dscratch0 // restore x8 from dscratch0
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dret // exit debug mode
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csrr x8, mhartid // get hart ID (0..3)
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sw x8, (DM_SREG_BASE+ACK_RES)(zero) // send resume-acknowledge
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csrr x8, dscratch0 // restore x8 from dscratch0
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dret // exit debug mode
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// execute program buffer
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// execute program buffer (implicit ebreak at the end of the buffer will bring us back to 'entry_normal')
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execute:
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sb zero, (DM_SREG_BASE+SREG_EXE_ACK)(zero) // ACK that execution is about to start
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csrr x8, dscratch0 // restore x8 from dscratch0
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fence.i // synchronize instruction fetch with memory (PBUF)
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jalr zero, zero, %lo(DM_PBUF_BASE) // jump to beginning of program buffer (PBUF)
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csrr x8, mhartid // get hart ID (0..3)
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sw x8, (DM_SREG_BASE+ACK_EXE)(zero) // send execute-acknowledge
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csrr x8, dscratch0 // restore x8 from dscratch0
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fence.i // synchronize instruction fetch with memory (PBUF)
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jalr zero, zero, %lo(DM_PBUF_BASE) // jump to beginning of program buffer (PBUF)
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// fill remaining ROM space with instructions that cause a debug-mode-internal exception
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unused:
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ecall // should never be reached
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unused: // should never be reached
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ecall
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ecall
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ecall
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ecall
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ecall
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ecall
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ecall
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ecall
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