github-mirrors/neorv32
1
0
Fork 0
mirror of https://github.com/stnolting/neorv32.git synced 2025-04-23 21:57:33 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

minor rtl code cleanups (#723)

Browse source
This commit is contained in:
stnolting 2023-11-09 18:03:55 +01:00 • committed by GitHub
commit 291fe91eb5
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
15 changed files with 35 additions and 49 deletions
Download patch file Download diff file Expand all files Collapse all files

1
CHANGELOG.md
View file

@ -32,6 +32,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
| Date (*dd.mm.yyyy*) | Version | Comment |
|:-------------------:|:-------:|:--------|
| 09.11.2023 | 1.9.0.8 | minor rtl code cleanups; [#723](https://github.com/stnolting/neorv32/pull/723) |
| 04.11.2023 | 1.9.0.7 | upgrade true random number generator to [neoTRNG version 3](https://github.com/stnolting/neoTRNG); [#721](https://github.com/stnolting/neorv32/pull/721) |
| 31.10.2023 | 1.9.0.6 | update crt0's early-boot trap handler; [#719](https://github.com/stnolting/neorv32/pull/719) |
| 30.10.2023 | 1.9.0.5 | minor rtl cleanups and code beautification; [#718](https://github.com/stnolting/neorv32/pull/718) |

3
rtl/core/mem/neorv32_dmem.default.vhd
View file

@ -65,9 +65,6 @@ begin
-- Sanity Checks --------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
assert not (is_power_of_two_f(DMEM_SIZE) = false) report
"NEORV32 PROCESSOR CONFIG ERROR: Internal DMEM size has to be a power of two!" severity error;
assert false report
"NEORV32 PROCESSOR CONFIG NOTE: Implementing DEFAULT processor-internal DMEM (RAM, " & natural'image(DMEM_SIZE) &
" bytes)." severity note;

3
rtl/core/mem/neorv32_dmem.legacy.vhd
View file

@ -66,9 +66,6 @@ begin
-- Sanity Checks --------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
assert not (is_power_of_two_f(DMEM_SIZE) = false) report
"NEORV32 PROCESSOR CONFIG ERROR: Internal DMEM size has to be a power of two!" severity error;
assert false report
"NEORV32 PROCESSOR CONFIG NOTE: Implementing LEGACY processor-internal DMEM (RAM, " & natural'image(DMEM_SIZE) &
" bytes)." severity note;

3
rtl/core/mem/neorv32_imem.default.vhd
View file

@ -82,9 +82,6 @@ begin
-- Sanity Checks --------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
assert not (is_power_of_two_f(IMEM_SIZE) = false) report
"NEORV32 PROCESSOR CONFIG ERROR: Internal IMEM size has to be a power of two!" severity error;
assert not (IMEM_AS_IROM = true) report
"NEORV32 PROCESSOR CONFIG NOTE: Implementing DEFAULT processor-internal IMEM as ROM (" & natural'image(IMEM_SIZE) &
" bytes), pre-initialized with application (" & natural'image(imem_app_size_c) & " bytes)." severity note;

3
rtl/core/mem/neorv32_imem.legacy.vhd
View file

@ -83,9 +83,6 @@ begin
-- Sanity Checks --------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
assert not (is_power_of_two_f(IMEM_SIZE) = false) report
"NEORV32 PROCESSOR CONFIG ERROR: Internal IMEM size has to be a power of two!" severity error;
assert not (IMEM_AS_IROM = true) report
"NEORV32 PROCESSOR CONFIG NOTE: Implementing LEGACY processor-internal IMEM as ROM (" & natural'image(IMEM_SIZE) &
" bytes), pre-initialized with application (" & natural'image(imem_app_size_c) & " bytes)." severity note;

4
rtl/core/neorv32_boot_rom.vhd
View file

@ -65,10 +65,8 @@ begin
-- Sanity Checks --------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
assert false report
"NEORV32 PROCESSOR CONFIG NOTE: Implementing internal bootloader ROM (" & natural'image(boot_rom_size_c) & " bytes)." severity note;
assert not (boot_rom_size_c > mem_boot_size_c) report
"NEORV32 PROCESSOR CONFIG ERROR! Boot ROM size out of range! Max " & natural'image(mem_boot_size_c) & " bytes." severity error;
"NEORV32 PROCESSOR CONFIG ERROR! Boot ROM size out of range!" severity error;
-- Memory Access --------------------------------------------------------------------------

2
rtl/core/neorv32_cpu_control.vhd
View file

@ -785,7 +785,7 @@ begin
-- Execute Engine FSM Comb ----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
execute_engine_fsm_comb: process(execute_engine, debug_ctrl, trap_ctrl, decode_aux, fetch_engine, issue_engine, csr, alu_cp_done_i, lsu_wait_i)
execute_engine_fsm_comb: process(execute_engine, debug_ctrl, trap_ctrl, decode_aux, issue_engine, csr, alu_cp_done_i, lsu_wait_i)
begin
-- arbiter defaults --
execute_engine.state_nxt <= execute_engine.state;

2
rtl/core/neorv32_cpu_cp_cfu.vhd
View file

@ -350,7 +350,7 @@ begin
control.result <= bit_rev_f(rs1_i);
control.done <= '1'; -- pure-combinatorial, so we are done "immediately"
when "001" => -- funct3 = "001": XNOR input operands
control.result <= rs1_i xnor rs2_i;
control.result <= not (rs1_i xor rs2_i);
control.done <= '1'; -- pure-combinatorial, so we are done "immediately"
when others => -- not implemented
control.result <= (others => '0');

4
rtl/core/neorv32_cpu_cp_fpu.vhd
View file

@ -567,7 +567,7 @@ begin
-- Min/Max Select (FMIN/FMAX) -------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
min_max_select: process(fpu_operands, comp_less_ff, fu_compare, ctrl_i)
min_max_select: process(fpu_operands, comp_less_ff, ctrl_i)
variable cond_v : std_ulogic_vector(2 downto 0);
begin
-- comparison result - check for special cases: -0 is less than +0
@ -576,7 +576,7 @@ begin
elsif ((fpu_operands.rs1_class(fp_class_pos_zero_c) = '1') and (fpu_operands.rs2_class(fp_class_neg_zero_c) = '1')) then
cond_v(0) := not ctrl_i.ir_funct3(0);
else -- "normal= comparison
cond_v(0) := comp_less_ff xnor ctrl_i.ir_funct3(0); -- min/max select
cond_v(0) := not (comp_less_ff xor ctrl_i.ir_funct3(0)); -- min/max select
end if;
-- number NaN check --

24
rtl/core/neorv32_debug_dm.vhd
View file

@ -86,18 +86,18 @@ architecture neorv32_debug_dm_rtl of neorv32_debug_dm is
-- **********************************************************
-- available DMI registers --
constant addr_data0_c : std_ulogic_vector(6 downto 0) := "000" & x"4";
constant addr_dmcontrol_c : std_ulogic_vector(6 downto 0) := "001" & x"0";
constant addr_dmstatus_c : std_ulogic_vector(6 downto 0) := "001" & x"1";
constant addr_hartinfo_c : std_ulogic_vector(6 downto 0) := "001" & x"2";
constant addr_abstractcs_c : std_ulogic_vector(6 downto 0) := "001" & x"6";
constant addr_command_c : std_ulogic_vector(6 downto 0) := "001" & x"7";
constant addr_abstractauto_c : std_ulogic_vector(6 downto 0) := "001" & x"8";
constant addr_nextdm_c : std_ulogic_vector(6 downto 0) := "001" & x"d";
constant addr_progbuf0_c : std_ulogic_vector(6 downto 0) := "010" & x"0";
constant addr_progbuf1_c : std_ulogic_vector(6 downto 0) := "010" & x"1";
constant addr_sbcs_c : std_ulogic_vector(6 downto 0) := "011" & x"8";
constant addr_haltsum0_c : std_ulogic_vector(6 downto 0) := "100" & x"0";
constant addr_data0_c : std_ulogic_vector(6 downto 0) := "0000100";
constant addr_dmcontrol_c : std_ulogic_vector(6 downto 0) := "0010000";
constant addr_dmstatus_c : std_ulogic_vector(6 downto 0) := "0010001";
constant addr_hartinfo_c : std_ulogic_vector(6 downto 0) := "0010010";
constant addr_abstractcs_c : std_ulogic_vector(6 downto 0) := "0010110";
constant addr_command_c : std_ulogic_vector(6 downto 0) := "0010111";
constant addr_abstractauto_c : std_ulogic_vector(6 downto 0) := "0011000";
constant addr_nextdm_c : std_ulogic_vector(6 downto 0) := "0011101";
constant addr_progbuf0_c : std_ulogic_vector(6 downto 0) := "0100000";
constant addr_progbuf1_c : std_ulogic_vector(6 downto 0) := "0100001";
constant addr_sbcs_c : std_ulogic_vector(6 downto 0) := "0111000";
constant addr_haltsum0_c : std_ulogic_vector(6 downto 0) := "1000000";
-- RISC-V 32-bit instruction prototypes --
constant instr_nop_c : std_ulogic_vector(31 downto 0) := x"00000013"; -- nop

14
rtl/core/neorv32_package.vhd
View file

@ -59,7 +59,7 @@ package neorv32_package is
-- Architecture Constants -----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01090007"; -- hardware version
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01090008"; -- hardware version
constant archid_c : natural := 19; -- official RISC-V architecture ID
constant XLEN : natural := 32; -- native data path width, do not change!
@ -646,7 +646,7 @@ package neorv32_package is
constant trap_db_halt_c : std_ulogic_vector(6 downto 0) := "1" & "1" & "00011"; -- 3: external halt request (async)
constant trap_db_step_c : std_ulogic_vector(6 downto 0) := "1" & "1" & "00100"; -- 4: single-stepping (async)
-- CPU Trap System ------------------------------------------------------------------------
-- Trap System ----------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- exception source bits --
constant exc_iaccess_c : natural := 0; -- instruction access fault
@ -659,8 +659,8 @@ package neorv32_package is
constant exc_saccess_c : natural := 7; -- store access fault
constant exc_laccess_c : natural := 8; -- load access fault
-- for debug mode only --
constant exc_db_break_c : natural := 9; -- enter debug mode via ebreak instruction ("sync EXCEPTION")
constant exc_db_hw_c : natural := 10; -- enter debug mode via hw trigger ("sync EXCEPTION")
constant exc_db_break_c : natural := 9; -- enter debug mode via ebreak instruction
constant exc_db_hw_c : natural := 10; -- enter debug mode via hw trigger
--
constant exc_width_c : natural := 11; -- length of this list in bits
-- interrupt source bits --
@ -684,12 +684,12 @@ package neorv32_package is
constant irq_firq_14_c : natural := 17; -- fast interrupt channel 14
constant irq_firq_15_c : natural := 18; -- fast interrupt channel 15
-- for debug mode only --
constant irq_db_halt_c : natural := 19; -- enter debug mode via external halt request ("async IRQ")
constant irq_db_step_c : natural := 20; -- enter debug mode via single-stepping ("async IRQ")
constant irq_db_halt_c : natural := 19; -- enter debug mode via external halt request
constant irq_db_step_c : natural := 20; -- enter debug mode via single-stepping
--
constant irq_width_c : natural := 21; -- length of this list in bits
-- CPU Privilege Modes --------------------------------------------------------------------
-- Privilege Modes ------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant priv_mode_m_c : std_ulogic := '1'; -- machine mode
constant priv_mode_u_c : std_ulogic := '0'; -- user mode

17
rtl/core/neorv32_trng.vhd
View file

@ -512,22 +512,18 @@ begin
sim_mode_false:
if SIM_MODE = false generate
assert false report
"[neoTRNG NOTE] Implementing physical entropy cell with " &
natural'image(NUM_INV) & " inverters." severity note;
-- ring oscillator --
ring_osc:
for i in 0 to NUM_INV-1 generate
ring_osc_start:
if (i = 0) generate
rosc(i) <= '0' when (en_i = '0') else (not rosc(NUM_INV-1)) when (sreg(i) = '1'); -- inverting latch
if (i = 0) generate -- inverting latch
rosc(i) <= '0' when (en_i = '0') else (not rosc(NUM_INV-1)) when (sreg(i) = '1') else rosc(i);
end generate;
ring_osc_chain:
if (i > 0) generate
rosc(i) <= '0' when (en_i = '0') else (not rosc(i-1)) when (sreg(i) = '1'); -- inverting latch
if (i > 0) generate -- inverting latch
rosc(i) <= '0' when (en_i = '0') else (not rosc(i-1)) when (sreg(i) = '1') else rosc(i);
end generate;
end generate;
@ -551,10 +547,11 @@ begin
if (rstn_i = '0') then
rosc <= (others => '0');
elsif rising_edge(clk_i) then
if (sreg(sreg'left) = '0') or (en_i = '0') then
if (en_i = '0') then
rosc <= (others => '0');
else -- sequence might NOT be maximum-length!
rosc <= rosc(rosc'left-1 downto 0) & (rosc(rosc'left) xnor rosc(0));
rosc(rosc'left downto 1) <= rosc(rosc'left-1 downto 0);
rosc(0) <= not (rosc(NUM_INV-1) xor rosc(0));
end if;
end if;
end process sim_lfsr;

2
rtl/core/neorv32_wishbone.vhd
View file

@ -118,7 +118,7 @@ begin
assert false report
"NEORV32 PROCESSOR CONFIG NOTE: Ext. Bus Interface - " &
cond_sel_string_f(PIPE_MODE, "PIPELINED", "CLASSIC/STANDARD") & " Wishbone protocol, " &
cond_sel_string_f(boolean(BUS_TIMEOUT /= 0), "auto-timeout (" & integer'image(BUS_TIMEOUT) & " cycles), ", "NO auto-timeout, ") &
cond_sel_string_f(boolean(BUS_TIMEOUT /= 0), "auto-timeout, ", "NO auto-timeout, ") &
cond_sel_string_f(BIG_ENDIAN, "BIG", "LITTLE") & "-endian byte order, " &
cond_sel_string_f(async_rx_c, "ASYNC ", "registered ") & "RX, " &
cond_sel_string_f(ASYNC_TX, "ASYNC ", "registered ") & "TX"

1
sim/neorv32_tb.vhd
View file

@ -49,6 +49,7 @@ use ieee.math_real.all;
library neorv32;
use neorv32.neorv32_package.all;
use neorv32.neorv32_application_image.all; -- this file is generated by the image generator
use std.textio.all;
library osvvm;

1
sim/simple/neorv32_tb.simple.vhd
View file

@ -44,6 +44,7 @@ use ieee.math_real.all;
library neorv32;
use neorv32.neorv32_package.all;
use neorv32.neorv32_application_image.all; -- this file is generated by the image generator
use std.textio.all;
entity neorv32_tb_simple is