mirror of
https://github.com/stnolting/neorv32.git
synced 2025-04-23 13:47:33 -04:00
Merge branch 'main' into sysinfo_ptr
Signed-off-by: Stephan <stnolting@gmail.com>
This commit is contained in:
Stephan
GitHub
commit
2b3712acbd
23 changed files with 230 additions and 253 deletions
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@ -305,10 +305,10 @@ int main(void) {
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// Configure machine system timer interrupt
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if (neorv32_mtime_available()) {
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NEORV32_MTIME.TIME_LO = 0;
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NEORV32_MTIME.TIME_HI = 0;
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NEORV32_MTIME.TIMECMP_LO = NEORV32_SYSINFO->CLK/4;
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NEORV32_MTIME.TIMECMP_HI = 0;
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NEORV32_MTIME->TIME_LO = 0;
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NEORV32_MTIME->TIME_HI = 0;
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NEORV32_MTIME->TIMECMP_LO = NEORV32_SYSINFO.CLK/4;
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NEORV32_MTIME->TIMECMP_HI = 0;
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neorv32_cpu_csr_write(CSR_MIE, 1 << CSR_MIE_MTIE); // activate MTIME IRQ source
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neorv32_cpu_csr_set(CSR_MSTATUS, 1 << CSR_MSTATUS_MIE); // enable machine-mode interrupts
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}
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@ -93,10 +93,10 @@ int main() {
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" simple data conversion functions using four memory-mapped registers.\n\n");
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neorv32_uart0_printf("Default CFS memory-mapped registers:\n"
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" * NEORV32_CFS.REG[0] (r/w): convert binary to gray code\n"
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" * NEORV32_CFS.REG[1] (r/w): convert gray to binary code\n"
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" * NEORV32_CFS.REG[2] (r/w): bit reversal\n"
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" * NEORV32_CFS.REG[3] (r/w): byte swap\n"
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" * NEORV32_CFS->REG[0] (r/w): convert binary to gray code\n"
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" * NEORV32_CFS->REG[1] (r/w): convert gray to binary code\n"
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" * NEORV32_CFS->REG[2] (r/w): bit reversal\n"
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" * NEORV32_CFS->REG[3] (r/w): byte swap\n"
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"The remaining 60 CFS registers are unused and will return 0 when read.\n");
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@ -104,29 +104,29 @@ int main() {
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neorv32_uart0_printf("\n--- CFS 'binary to gray' function ---\n");
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for (i=0; i<TESTCASES; i++) {
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tmp = xorshift32(); // get random test data
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NEORV32_CFS.REG[0] = tmp; // write to CFS memory-mapped register 0
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neorv32_uart0_printf("%u: IN = 0x%x, OUT = 0x%x\n", i, tmp, NEORV32_CFS.REG[0]); // read from CFS memory-mapped register 0
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NEORV32_CFS->REG[0] = tmp; // write to CFS memory-mapped register 0
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neorv32_uart0_printf("%u: IN = 0x%x, OUT = 0x%x\n", i, tmp, NEORV32_CFS->REG[0]); // read from CFS memory-mapped register 0
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}
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neorv32_uart0_printf("\n--- CFS 'gray to binary' function ---\n");
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for (i=0; i<TESTCASES; i++) {
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tmp = xorshift32(); // get random test data
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NEORV32_CFS.REG[1] = tmp; // write to CFS memory-mapped register 1
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neorv32_uart0_printf("%u: IN = 0x%x, OUT = 0x%x\n", i, tmp, NEORV32_CFS.REG[1]); // read from CFS memory-mapped register 1
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NEORV32_CFS->REG[1] = tmp; // write to CFS memory-mapped register 1
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neorv32_uart0_printf("%u: IN = 0x%x, OUT = 0x%x\n", i, tmp, NEORV32_CFS->REG[1]); // read from CFS memory-mapped register 1
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}
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neorv32_uart0_printf("\n--- CFS 'bit reversal' function ---\n");
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for (i=0; i<TESTCASES; i++) {
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tmp = xorshift32(); // get random test data
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NEORV32_CFS.REG[2] = tmp; // write to CFS memory-mapped register 2
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neorv32_uart0_printf("%u: IN = 0x%x, OUT = 0x%x\n", i, tmp, NEORV32_CFS.REG[2]); // read from CFS memory-mapped register 2
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NEORV32_CFS->REG[2] = tmp; // write to CFS memory-mapped register 2
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neorv32_uart0_printf("%u: IN = 0x%x, OUT = 0x%x\n", i, tmp, NEORV32_CFS->REG[2]); // read from CFS memory-mapped register 2
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}
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neorv32_uart0_printf("\n--- CFS 'byte swap' function ---\n");
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for (i=0; i<TESTCASES; i++) {
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tmp = xorshift32(); // get random test data
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NEORV32_CFS.REG[3] = tmp; // write to CFS memory-mapped register 3
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neorv32_uart0_printf("%u: IN = 0x%x, OUT = 0x%x\n", i, tmp, NEORV32_CFS.REG[3]); // read from CFS memory-mapped register 3
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NEORV32_CFS->REG[3] = tmp; // write to CFS memory-mapped register 3
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neorv32_uart0_printf("%u: IN = 0x%x, OUT = 0x%x\n", i, tmp, NEORV32_CFS->REG[3]); // read from CFS memory-mapped register 3
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}
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@ -102,7 +102,7 @@ int main() {
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// check NEOLED configuration
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neorv32_uart0_printf("Checking NEOLED configuration:\n"
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" Hardware FIFO size: %u entries\n"
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" Control register: 0x%x\n\n", neorv32_neoled_get_buffer_size(), NEORV32_NEOLED.CTRL);
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" Control register: 0x%x\n\n", neorv32_neoled_get_buffer_size(), NEORV32_NEOLED->CTRL);
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// clear all LEDs
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@ -104,7 +104,7 @@ int main() {
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"Type 'help' to see the help menu.\n\n");
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// disable and reset SPI module
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NEORV32_SPI.CTRL = 0;
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NEORV32_SPI->CTRL = 0;
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spi_configured = 0; // SPI not configured yet
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spi_size = 0;
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@ -82,7 +82,7 @@ void neorv32_spi_isr(t_neorv32_spi *self) {
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case 1: // uint8_t
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// read data from SPI from last transfer
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for ( ; self->uint32Read<self->uint32Write; (self->uint32Read)++ ) {
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((uint8_t *) self->ptrSpiBuf)[self->uint32Read] = (uint8_t) (NEORV32_SPI.DATA & 0xff); // capture from last transfer
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((uint8_t *) self->ptrSpiBuf)[self->uint32Read] = (uint8_t) (NEORV32_SPI->DATA & 0xff); // capture from last transfer
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}
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if ( self->uint32Read == self->uint32Total ) { // transfer done, no new data
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neorv32_spi_cs_dis(); // deselect slave
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@ -95,13 +95,13 @@ void neorv32_spi_isr(t_neorv32_spi *self) {
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for ( ; self->uint32Write<uint32Lim; (self->uint32Write)++ ) {
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uint32Buf = 0;
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uint32Buf |= ((uint8_t *) self->ptrSpiBuf)[self->uint32Write];
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NEORV32_SPI.DATA = uint32Buf; // next transfer
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NEORV32_SPI->DATA = uint32Buf; // next transfer
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}
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break;
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case 2: // uint16_t
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// read data from SPI from last transfer
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for ( ; self->uint32Read<self->uint32Write; (self->uint32Read)++ ) {
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((uint16_t *) self->ptrSpiBuf)[self->uint32Read] = (uint16_t) (NEORV32_SPI.DATA & 0xffff); // capture from last transfer
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((uint16_t *) self->ptrSpiBuf)[self->uint32Read] = (uint16_t) (NEORV32_SPI->DATA & 0xffff); // capture from last transfer
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}
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if ( self->uint32Read == self->uint32Total ) { // transfer done, no new data
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neorv32_spi_cs_dis(); // deselect slave
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@ -114,13 +114,13 @@ void neorv32_spi_isr(t_neorv32_spi *self) {
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for ( ; self->uint32Write<uint32Lim; (self->uint32Write)++ ) {
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uint32Buf = 0;
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uint32Buf |= ((uint16_t *) self->ptrSpiBuf)[self->uint32Write];
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NEORV32_SPI.DATA = uint32Buf; // next transfer
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NEORV32_SPI->DATA = uint32Buf; // next transfer
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}
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break;
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case 4: // uint32_t
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// read data from SPI from last transfer
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for ( ; self->uint32Read<self->uint32Write; (self->uint32Read)++ ) {
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((uint32_t *) self->ptrSpiBuf)[self->uint32Read] = NEORV32_SPI.DATA; // capture from last transfer
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((uint32_t *) self->ptrSpiBuf)[self->uint32Read] = NEORV32_SPI->DATA; // capture from last transfer
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}
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if ( self->uint32Read == self->uint32Total ) { // transfer done, no new data
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neorv32_spi_cs_dis(); // deselect slave
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@ -133,7 +133,7 @@ void neorv32_spi_isr(t_neorv32_spi *self) {
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for ( ; self->uint32Write<uint32Lim; (self->uint32Write)++ ) {
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uint32Buf = 0;
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uint32Buf |= ((uint32_t *) self->ptrSpiBuf)[self->uint32Write];
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NEORV32_SPI.DATA = uint32Buf; // next transfer
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NEORV32_SPI->DATA = uint32Buf; // next transfer
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}
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break;
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default: // unknown
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@ -189,7 +189,7 @@ int neorv32_spi_rw(t_neorv32_spi *self, void *spi, uint8_t csn, uint32_t num_ele
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return 2; // unsupported byte size
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}
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(self->uint32Write)++;
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NEORV32_SPI.DATA = uint32Buf; // next transfer
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NEORV32_SPI->DATA = uint32Buf; // next transfer
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return 0; // successful end
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}
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@ -247,7 +247,7 @@ void scan_twi(void) {
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**************************************************************************/
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void check_claimed(void) {
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if (NEORV32_TWI.CTRL & (1 << TWI_CTRL_CLAIMED)) {
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if (NEORV32_TWI->CTRL & (1 << TWI_CTRL_CLAIMED)) {
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if (bus_claimed == 0) {
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neorv32_uart0_printf("Bus claimed by another controller.\n");
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}
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@ -267,9 +267,9 @@ void check_claimed(void) {
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void toggle_mack(void) {
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// toggle MACK flag
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NEORV32_TWI.CTRL ^= 1 << TWI_CTRL_MACK;
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NEORV32_TWI->CTRL ^= 1 << TWI_CTRL_MACK;
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if (NEORV32_TWI.CTRL & (1 << TWI_CTRL_MACK)) {
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if (NEORV32_TWI->CTRL & (1 << TWI_CTRL_MACK)) {
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neorv32_uart0_printf("MACK enabled.\n");
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}
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else {
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@ -690,7 +690,7 @@ int main() {
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if ((neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_L_ACCESS) && // load bus access error exception
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(neorv32_cpu_csr_read(CSR_MTVAL) == ADDR_UNREACHABLE) &&
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(tmp_b == 0xcafe1230) && // make sure dest. reg is not updated
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(NEORV32_BUSKEEPER.CTRL = tmp_a)) { // buskeeper: error flag + timeout error
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(NEORV32_BUSKEEPER->CTRL = tmp_a)) { // buskeeper: error flag + timeout error
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test_ok();
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}
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else {
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@ -739,7 +739,7 @@ int main() {
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if ((neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_S_ACCESS) && // store bus access error exception
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(neorv32_cpu_csr_read(CSR_MTVAL) == ADDR_READONLY) &&
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(NEORV32_BUSKEEPER.CTRL == tmp_a)) { // buskeeper: error flag + device error
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(NEORV32_BUSKEEPER->CTRL == tmp_a)) { // buskeeper: error flag + device error
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test_ok();
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}
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else {
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@ -947,7 +947,7 @@ int main() {
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asm volatile ("wfi");
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neorv32_cpu_csr_write(CSR_MIE, 0);
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NEORV32_WDT.CTRL = 0;
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NEORV32_WDT->CTRL = 0;
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if (neorv32_cpu_csr_read(CSR_MCAUSE) == WDT_TRAP_CODE) {
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test_ok();
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@ -1231,8 +1231,8 @@ int main() {
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test_fail();
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}
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NEORV32_XIRQ.IER = 0;
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NEORV32_XIRQ.IPR = -1;
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NEORV32_XIRQ->IER = 0;
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NEORV32_XIRQ->IPR = -1;
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// ----------------------------------------------------------
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@ -1660,7 +1660,7 @@ int main() {
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**************************************************************************/
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void sim_irq_trigger(uint32_t sel) {
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*(IO_REG32 (0xFF000000)) = sel;
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*((volatile uint32_t*) (0xFF000000)) = sel;
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}
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@ -675,7 +675,7 @@ enum NEORV32_CLOCK_PRSC_enum {
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// ############################################################################################################################
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/**@{*/
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/** on-chip debugger - debug module prototype */
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typedef struct __attribute__((packed,aligned(4))) {
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typedef volatile struct __attribute__((packed,aligned(4))) {
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const uint32_t CODE[16]; /**< offset 0: park loop code ROM (r/-) */
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const uint32_t PBUF[4]; /**< offset 64: program buffer (r/-) */
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const uint32_t reserved1[12]; /**< reserved */
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@ -689,7 +689,7 @@ typedef struct __attribute__((packed,aligned(4))) {
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#define NEORV32_DM_BASE (0XFFFFF800U)
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/** on-chip debugger debug module hardware access (#neorv32_dm_t) */
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#define NEORV32_DM (*((volatile neorv32_dm_t*) (NEORV32_DM_BASE)))
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#define NEORV32_DM ((neorv32_dm_t*) (NEORV32_DM_BASE))
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/**@}*/
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@ -698,35 +698,12 @@ typedef struct __attribute__((packed,aligned(4))) {
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// ############################################################################################################################
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/**********************************************************************//**
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* @name Helper macros for easy memory-mapped register access (DEPRECATED!)
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**************************************************************************/
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/**@{*/
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/** memory-mapped byte (8-bit) read/write register */
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#define IO_REG8 (volatile uint8_t*)
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/** memory-mapped half-word (16-bit) read/write register */
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#define IO_REG16 (volatile uint16_t*)
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/** memory-mapped word (32-bit) read/write register */
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#define IO_REG32 (volatile uint32_t*)
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/** memory-mapped double-word (64-bit) read/write register */
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#define IO_REG64 (volatile uint64_t*)
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/** memory-mapped byte (8-bit) read-only register */
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#define IO_ROM8 (const volatile uint8_t*)
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/** memory-mapped half-word (16-bit) read-only register */
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#define IO_ROM16 (const volatile uint16_t*)
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/** memory-mapped word (32-bit) read-only register */
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#define IO_ROM32 (const volatile uint32_t*)
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/** memory-mapped double-word (64-bit) read-only register */
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#define IO_ROM64 (const volatile uint64_t*)
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/**@}*/
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/**********************************************************************//**
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* @name IO Device: Custom Functions Subsystem (CFS)
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**************************************************************************/
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/**@{*/
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/** CFS module prototype */
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typedef struct __attribute__((packed,aligned(4))) {
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typedef volatile struct __attribute__((packed,aligned(4))) {
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uint32_t REG[64]; /**< offset 4*0..4*63: CFS register 0..63, user-defined */
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} neorv32_cfs_t;
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@ -734,7 +711,7 @@ typedef struct __attribute__((packed,aligned(4))) {
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#define NEORV32_CFS_BASE (0xFFFFFE00U)
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/** CFS module hardware access (#neorv32_cfs_t) */
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#define NEORV32_CFS (*((volatile neorv32_cfs_t*) (NEORV32_CFS_BASE)))
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#define NEORV32_CFS ((neorv32_cfs_t*) (NEORV32_CFS_BASE))
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/**@}*/
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@ -743,7 +720,7 @@ typedef struct __attribute__((packed,aligned(4))) {
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**************************************************************************/
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/**@{*/
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/** SDI module prototype */
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typedef struct __attribute__((packed,aligned(4))) {
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typedef volatile struct __attribute__((packed,aligned(4))) {
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uint32_t CTRL; /**< offset 0: control register (#NEORV32_SDI_CTRL_enum) */
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uint32_t DATA; /**< offset 4: data register */
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} neorv32_sdi_t;
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@ -752,7 +729,7 @@ typedef struct __attribute__((packed,aligned(4))) {
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#define NEORV32_SDI_BASE (0xFFFFFF00U)
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/** SDI module hardware access (#neorv32_sdi_t) */
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#define NEORV32_SDI (*((volatile neorv32_sdi_t*) (NEORV32_SDI_BASE)))
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#define NEORV32_SDI ((neorv32_sdi_t*) (NEORV32_SDI_BASE))
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/** SDI control register bits */
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enum NEORV32_SDI_CTRL_enum {
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@ -781,7 +758,7 @@ enum NEORV32_SDI_CTRL_enum {
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**************************************************************************/
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/**@{*/
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/** XIP module prototype */
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typedef struct __attribute__((packed,aligned(4))) {
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typedef volatile struct __attribute__((packed,aligned(4))) {
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uint32_t CTRL; /**< offset 0: control register (#NEORV32_XIP_CTRL_enum) */
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const uint32_t reserved; /**< offset 4: reserved */
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uint32_t DATA_LO; /**< offset 8: SPI data register low */
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@ -792,7 +769,7 @@ typedef struct __attribute__((packed,aligned(4))) {
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#define NEORV32_XIP_BASE (0xFFFFFF40U)
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/** XIP module hardware access (#neorv32_xip_t) */
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#define NEORV32_XIP (*((volatile neorv32_xip_t*) (NEORV32_XIP_BASE)))
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#define NEORV32_XIP ((neorv32_xip_t*) (NEORV32_XIP_BASE))
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/** XIP control/data register bits */
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enum NEORV32_XIP_CTRL_enum {
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@ -826,7 +803,7 @@ enum NEORV32_XIP_CTRL_enum {
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**************************************************************************/
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/**@{*/
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/** PWM module prototype */
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typedef struct __attribute__((packed,aligned(4))) {
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typedef volatile struct __attribute__((packed,aligned(4))) {
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uint32_t CTRL; /**< offset 0: control register (#NEORV32_PWM_CTRL_enum) */
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uint32_t DC[3]; /**< offset 4..12: duty cycle register 0..2 */
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} neorv32_pwm_t;
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@ -835,7 +812,7 @@ typedef struct __attribute__((packed,aligned(4))) {
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#define NEORV32_PWM_BASE (0xFFFFFF50U)
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/** PWM module hardware access (#neorv32_pwm_t) */
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#define NEORV32_PWM (*((volatile neorv32_pwm_t*) (NEORV32_PWM_BASE)))
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#define NEORV32_PWM ((neorv32_pwm_t*) (NEORV32_PWM_BASE))
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/** PWM control register bits */
|
||||
enum NEORV32_PWM_CTRL_enum {
|
||||
|
|
@ -852,7 +829,7 @@ enum NEORV32_PWM_CTRL_enum {
|
|||
**************************************************************************/
|
||||
/**@{*/
|
||||
/** GPTMR module prototype */
|
||||
typedef struct __attribute__((packed,aligned(4))) {
|
||||
typedef volatile struct __attribute__((packed,aligned(4))) {
|
||||
uint32_t CTRL; /**< offset 0: control register (#NEORV32_GPTMR_CTRL_enum) */
|
||||
uint32_t THRES; /**< offset 4: threshold register */
|
||||
uint32_t COUNT; /**< offset 8: counter register */
|
||||
|
|
@ -863,7 +840,7 @@ typedef struct __attribute__((packed,aligned(4))) {
|
|||
#define NEORV32_GPTMR_BASE (0xFFFFFF60U)
|
||||
|
||||
/** GPTMR module hardware access (#neorv32_gptmr_t) */
|
||||
#define NEORV32_GPTMR (*((volatile neorv32_gptmr_t*) (NEORV32_GPTMR_BASE)))
|
||||
#define NEORV32_GPTMR ((neorv32_gptmr_t*) (NEORV32_GPTMR_BASE))
|
||||
|
||||
/** GPTMR control/data register bits */
|
||||
enum NEORV32_GPTMR_CTRL_enum {
|
||||
|
|
@ -881,7 +858,7 @@ enum NEORV32_GPTMR_CTRL_enum {
|
|||
**************************************************************************/
|
||||
/**@{*/
|
||||
/** ONEWIRE module prototype */
|
||||
typedef struct __attribute__((packed,aligned(4))) {
|
||||
typedef volatile struct __attribute__((packed,aligned(4))) {
|
||||
uint32_t CTRL; /**< offset 0: control register (#NEORV32_ONEWIRE_CTRL_enum) */
|
||||
uint32_t DATA; /**< offset 4: transmission data register (#NEORV32_ONEWIRE_DATA_enum) */
|
||||
} neorv32_onewire_t;
|
||||
|
|
@ -890,7 +867,7 @@ typedef struct __attribute__((packed,aligned(4))) {
|
|||
#define NEORV32_ONEWIRE_BASE (0xFFFFFF70U)
|
||||
|
||||
/** ONEWIRE module hardware access (#neorv32_onewire_t) */
|
||||
#define NEORV32_ONEWIRE (*((volatile neorv32_onewire_t*) (NEORV32_ONEWIRE_BASE)))
|
||||
#define NEORV32_ONEWIRE ((neorv32_onewire_t*) (NEORV32_ONEWIRE_BASE))
|
||||
|
||||
/** ONEWIRE control register bits */
|
||||
enum NEORV32_ONEWIRE_CTRL_enum {
|
||||
|
|
@ -927,7 +904,7 @@ enum NEORV32_ONEWIRE_DATA_enum {
|
|||
**************************************************************************/
|
||||
/**@{*/
|
||||
/** BUSKEEPER module prototype */
|
||||
typedef struct __attribute__((packed,aligned(4))) {
|
||||
typedef volatile struct __attribute__((packed,aligned(4))) {
|
||||
uint32_t CTRL; /**< offset 0: control register (#NEORV32_BUSKEEPER_CTRL_enum) */
|
||||
const uint32_t reserved ; /**< offset 4: reserved */
|
||||
} neorv32_buskeeper_t;
|
||||
|
|
@ -936,7 +913,7 @@ typedef struct __attribute__((packed,aligned(4))) {
|
|||
#define NEORV32_BUSKEEPER_BASE (0xFFFFFF78U)
|
||||
|
||||
/** BUSKEEPER module hardware access (#neorv32_buskeeper_t) */
|
||||
#define NEORV32_BUSKEEPER (*((volatile neorv32_buskeeper_t*) (NEORV32_BUSKEEPER_BASE)))
|
||||
#define NEORV32_BUSKEEPER ((neorv32_buskeeper_t*) (NEORV32_BUSKEEPER_BASE))
|
||||
|
||||
/** BUSKEEPER control/data register bits */
|
||||
enum NEORV32_BUSKEEPER_CTRL_enum {
|
||||
|
|
@ -951,7 +928,7 @@ enum NEORV32_BUSKEEPER_CTRL_enum {
|
|||
**************************************************************************/
|
||||
/**@{*/
|
||||
/** XIRQ module prototype */
|
||||
typedef struct __attribute__((packed,aligned(4))) {
|
||||
typedef volatile struct __attribute__((packed,aligned(4))) {
|
||||
uint32_t IER; /**< offset 0: IRQ input enable register */
|
||||
uint32_t IPR; /**< offset 4: pending IRQ register /ack/clear */
|
||||
uint32_t SCR; /**< offset 8: interrupt source register */
|
||||
|
|
@ -962,7 +939,7 @@ typedef struct __attribute__((packed,aligned(4))) {
|
|||
#define NEORV32_XIRQ_BASE (0xFFFFFF80U)
|
||||
|
||||
/** XIRQ module hardware access (#neorv32_xirq_t) */
|
||||
#define NEORV32_XIRQ (*((volatile neorv32_xirq_t*) (NEORV32_XIRQ_BASE)))
|
||||
#define NEORV32_XIRQ ((neorv32_xirq_t*) (NEORV32_XIRQ_BASE))
|
||||
/**@}*/
|
||||
|
||||
|
||||
|
|
@ -971,7 +948,7 @@ typedef struct __attribute__((packed,aligned(4))) {
|
|||
**************************************************************************/
|
||||
/**@{*/
|
||||
/** MTIME module prototype */
|
||||
typedef struct __attribute__((packed,aligned(4))) {
|
||||
typedef volatile struct __attribute__((packed,aligned(4))) {
|
||||
uint32_t TIME_LO; /**< offset 0: time register low word */
|
||||
uint32_t TIME_HI; /**< offset 4: time register high word */
|
||||
uint32_t TIMECMP_LO; /**< offset 8: compare register low word */
|
||||
|
|
@ -982,7 +959,7 @@ typedef struct __attribute__((packed,aligned(4))) {
|
|||
#define NEORV32_MTIME_BASE (0xFFFFFF90U)
|
||||
|
||||
/** MTIME module hardware access (#neorv32_mtime_t) */
|
||||
#define NEORV32_MTIME (*((volatile neorv32_mtime_t*) (NEORV32_MTIME_BASE)))
|
||||
#define NEORV32_MTIME ((neorv32_mtime_t*) (NEORV32_MTIME_BASE))
|
||||
/**@}*/
|
||||
|
||||
|
||||
|
|
@ -1077,7 +1054,7 @@ enum NEORV32_UART_DATA_enum {
|
|||
**************************************************************************/
|
||||
/**@{*/
|
||||
/** SPI module prototype */
|
||||
typedef struct __attribute__((packed,aligned(4))) {
|
||||
typedef volatile struct __attribute__((packed,aligned(4))) {
|
||||
uint32_t CTRL; /**< offset 0: control register (#NEORV32_SPI_CTRL_enum) */
|
||||
uint32_t DATA; /**< offset 4: data register */
|
||||
} neorv32_spi_t;
|
||||
|
|
@ -1086,7 +1063,7 @@ typedef struct __attribute__((packed,aligned(4))) {
|
|||
#define NEORV32_SPI_BASE (0xFFFFFFA8U)
|
||||
|
||||
/** SPI module hardware access (#neorv32_spi_t) */
|
||||
#define NEORV32_SPI (*((volatile neorv32_spi_t*) (NEORV32_SPI_BASE)))
|
||||
#define NEORV32_SPI ((neorv32_spi_t*) (NEORV32_SPI_BASE))
|
||||
|
||||
/** SPI control register bits */
|
||||
enum NEORV32_SPI_CTRL_enum {
|
||||
|
|
@ -1125,7 +1102,7 @@ enum NEORV32_SPI_CTRL_enum {
|
|||
**************************************************************************/
|
||||
/**@{*/
|
||||
/** TWI module prototype */
|
||||
typedef struct __attribute__((packed,aligned(4))) {
|
||||
typedef volatile struct __attribute__((packed,aligned(4))) {
|
||||
uint32_t CTRL; /**< offset 0: control register (#NEORV32_TWI_CTRL_enum) */
|
||||
uint32_t DATA; /**< offset 4: data register (#NEORV32_TWI_DATA_enum) */
|
||||
} neorv32_twi_t;
|
||||
|
|
@ -1134,7 +1111,7 @@ typedef struct __attribute__((packed,aligned(4))) {
|
|||
#define NEORV32_TWI_BASE (0xFFFFFFB0U)
|
||||
|
||||
/** TWI module hardware access (#neorv32_twi_t) */
|
||||
#define NEORV32_TWI (*((volatile neorv32_twi_t*) (NEORV32_TWI_BASE)))
|
||||
#define NEORV32_TWI ((neorv32_twi_t*) (NEORV32_TWI_BASE))
|
||||
|
||||
/** TWI control register bits */
|
||||
enum NEORV32_TWI_CTRL_enum {
|
||||
|
|
@ -1169,7 +1146,7 @@ enum NEORV32_TWI_DATA_enum {
|
|||
**************************************************************************/
|
||||
/**@{*/
|
||||
/** TRNG module prototype */
|
||||
typedef struct __attribute__((packed,aligned(4))) {
|
||||
typedef volatile struct __attribute__((packed,aligned(4))) {
|
||||
uint32_t CTRL; /**< offset 0: control register (#NEORV32_TRNG_CTRL_enum) */
|
||||
} neorv32_trng_t;
|
||||
|
||||
|
|
@ -1177,7 +1154,7 @@ typedef struct __attribute__((packed,aligned(4))) {
|
|||
#define NEORV32_TRNG_BASE (0xFFFFFFB8U)
|
||||
|
||||
/** TRNG module hardware access (#neorv32_trng_t) */
|
||||
#define NEORV32_TRNG (*((volatile neorv32_trng_t*) (NEORV32_TRNG_BASE)))
|
||||
#define NEORV32_TRNG ((neorv32_trng_t*) (NEORV32_TRNG_BASE))
|
||||
|
||||
/** TRNG control/data register bits */
|
||||
enum NEORV32_TRNG_CTRL_enum {
|
||||
|
|
@ -1197,7 +1174,7 @@ enum NEORV32_TRNG_CTRL_enum {
|
|||
**************************************************************************/
|
||||
/**@{*/
|
||||
/** WDT module prototype */
|
||||
typedef struct __attribute__((packed,aligned(4))) {
|
||||
typedef volatile struct __attribute__((packed,aligned(4))) {
|
||||
uint32_t CTRL; /**< offset 0: control register (#NEORV32_WDT_CTRL_enum) */
|
||||
} neorv32_wdt_t;
|
||||
|
||||
|
|
@ -1205,7 +1182,7 @@ typedef struct __attribute__((packed,aligned(4))) {
|
|||
#define NEORV32_WDT_BASE (0xFFFFFFBCU)
|
||||
|
||||
/** WDT module hardware access (#neorv32_wdt_t) */
|
||||
#define NEORV32_WDT (*((volatile neorv32_wdt_t*) (NEORV32_WDT_BASE)))
|
||||
#define NEORV32_WDT ((neorv32_wdt_t*) (NEORV32_WDT_BASE))
|
||||
|
||||
/** WDT control register bits */
|
||||
enum NEORV32_WDT_CTRL_enum {
|
||||
|
|
@ -1227,7 +1204,7 @@ enum NEORV32_WDT_CTRL_enum {
|
|||
**************************************************************************/
|
||||
/**@{*/
|
||||
/** GPIO module prototype */
|
||||
typedef struct __attribute__((packed,aligned(4))) {
|
||||
typedef volatile struct __attribute__((packed,aligned(4))) {
|
||||
const uint32_t INPUT_LO; /**< offset 0: parallel input port lower 32-bit, read-only */
|
||||
const uint32_t INPUT_HI; /**< offset 4: parallel input port upper 32-bit, read-only */
|
||||
uint32_t OUTPUT_LO; /**< offset 8: parallel output port lower 32-bit */
|
||||
|
|
@ -1238,7 +1215,7 @@ typedef struct __attribute__((packed,aligned(4))) {
|
|||
#define NEORV32_GPIO_BASE (0xFFFFFFC0U)
|
||||
|
||||
/** GPIO module hardware access (#neorv32_gpio_t) */
|
||||
#define NEORV32_GPIO (*((volatile neorv32_gpio_t*) (NEORV32_GPIO_BASE)))
|
||||
#define NEORV32_GPIO ((neorv32_gpio_t*) (NEORV32_GPIO_BASE))
|
||||
/**@}*/
|
||||
|
||||
|
||||
|
|
@ -1247,7 +1224,7 @@ typedef struct __attribute__((packed,aligned(4))) {
|
|||
**************************************************************************/
|
||||
/**@{*/
|
||||
/** NEOLED module prototype */
|
||||
typedef struct __attribute__((packed,aligned(4))) {
|
||||
typedef volatile struct __attribute__((packed,aligned(4))) {
|
||||
uint32_t CTRL; /**< offset 0: control register */
|
||||
uint32_t DATA; /**< offset 4: data register (#NEORV32_NEOLED_CTRL_enum) */
|
||||
} neorv32_neoled_t;
|
||||
|
|
@ -1256,7 +1233,7 @@ typedef struct __attribute__((packed,aligned(4))) {
|
|||
#define NEORV32_NEOLED_BASE (0xFFFFFFD8U)
|
||||
|
||||
/** NEOLED module hardware access (#neorv32_neoled_t) */
|
||||
#define NEORV32_NEOLED (*((volatile neorv32_neoled_t*) (NEORV32_NEOLED_BASE)))
|
||||
#define NEORV32_NEOLED ((neorv32_neoled_t*) (NEORV32_NEOLED_BASE))
|
||||
|
||||
/** NEOLED control register bits */
|
||||
enum NEORV32_NEOLED_CTRL_enum {
|
||||
|
|
|
|||
|
|
@ -65,7 +65,7 @@ uint32_t neorv32_neoled_get_buffer_size(void);
|
|||
**************************************************************************/
|
||||
inline void __attribute__ ((always_inline)) neorv32_neoled_write_nonblocking(uint32_t data) {
|
||||
|
||||
NEORV32_NEOLED.DATA = data; // send new LED data
|
||||
NEORV32_NEOLED->DATA = data; // send new LED data
|
||||
}
|
||||
|
||||
#endif // neorv32_neoled_h
|
||||
|
|
|
|||
|
|
@ -70,10 +70,10 @@ void neorv32_gpio_pin_set(int pin) {
|
|||
uint32_t mask = (uint32_t)(1 << (pin & 0x1f));
|
||||
|
||||
if (pin < 32) {
|
||||
NEORV32_GPIO.OUTPUT_LO |= mask;
|
||||
NEORV32_GPIO->OUTPUT_LO |= mask;
|
||||
}
|
||||
else {
|
||||
NEORV32_GPIO.OUTPUT_HI |= mask;
|
||||
NEORV32_GPIO->OUTPUT_HI |= mask;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -88,10 +88,10 @@ void neorv32_gpio_pin_clr(int pin) {
|
|||
uint32_t mask = (uint32_t)(1 << (pin & 0x1f));
|
||||
|
||||
if (pin < 32) {
|
||||
NEORV32_GPIO.OUTPUT_LO &= ~mask;
|
||||
NEORV32_GPIO->OUTPUT_LO &= ~mask;
|
||||
}
|
||||
else {
|
||||
NEORV32_GPIO.OUTPUT_HI &= ~mask;
|
||||
NEORV32_GPIO->OUTPUT_HI &= ~mask;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -106,10 +106,10 @@ void neorv32_gpio_pin_toggle(int pin) {
|
|||
uint32_t mask = (uint32_t)(1 << (pin & 0x1f));
|
||||
|
||||
if (pin < 32) {
|
||||
NEORV32_GPIO.OUTPUT_LO ^= mask;
|
||||
NEORV32_GPIO->OUTPUT_LO ^= mask;
|
||||
}
|
||||
else {
|
||||
NEORV32_GPIO.OUTPUT_HI ^= mask;
|
||||
NEORV32_GPIO->OUTPUT_HI ^= mask;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -125,10 +125,10 @@ uint32_t neorv32_gpio_pin_get(int pin) {
|
|||
uint32_t mask = (uint32_t)(1 << (pin & 0x1f));
|
||||
|
||||
if (pin < 32) {
|
||||
return NEORV32_GPIO.INPUT_LO & mask;
|
||||
return NEORV32_GPIO->INPUT_LO & mask;
|
||||
}
|
||||
else {
|
||||
return NEORV32_GPIO.INPUT_HI & mask;
|
||||
return NEORV32_GPIO->INPUT_HI & mask;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -146,8 +146,8 @@ void neorv32_gpio_port_set(uint64_t port_data) {
|
|||
} data;
|
||||
|
||||
data.uint64 = port_data;
|
||||
NEORV32_GPIO.OUTPUT_LO = data.uint32[0];
|
||||
NEORV32_GPIO.OUTPUT_HI = data.uint32[1];
|
||||
NEORV32_GPIO->OUTPUT_LO = data.uint32[0];
|
||||
NEORV32_GPIO->OUTPUT_HI = data.uint32[1];
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -163,8 +163,8 @@ uint64_t neorv32_gpio_port_get(void) {
|
|||
uint32_t uint32[sizeof(uint64_t)/sizeof(uint32_t)];
|
||||
} data;
|
||||
|
||||
data.uint32[0] = NEORV32_GPIO.INPUT_LO;
|
||||
data.uint32[1] = NEORV32_GPIO.INPUT_HI;
|
||||
data.uint32[0] = NEORV32_GPIO->INPUT_LO;
|
||||
data.uint32[1] = NEORV32_GPIO->INPUT_HI;
|
||||
|
||||
return data.uint64;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -69,16 +69,16 @@ int neorv32_gptmr_available(void) {
|
|||
**************************************************************************/
|
||||
void neorv32_gptmr_setup(int prsc, int mode, uint32_t threshold) {
|
||||
|
||||
NEORV32_GPTMR.CTRL = 0; // reset
|
||||
NEORV32_GPTMR.THRES = threshold;
|
||||
NEORV32_GPTMR.COUNT = 0; // reset counter
|
||||
NEORV32_GPTMR->CTRL = 0; // reset
|
||||
NEORV32_GPTMR->THRES = threshold;
|
||||
NEORV32_GPTMR->COUNT = 0; // reset counter
|
||||
|
||||
uint32_t tmp = 0;
|
||||
tmp |= (uint32_t)(1 & 0x01) << GPTMR_CTRL_EN;
|
||||
tmp |= (uint32_t)(prsc & 0x07) << GPTMR_CTRL_PRSC0;
|
||||
tmp |= (uint32_t)(mode & 0x01) << GPTMR_CTRL_MODE;
|
||||
|
||||
NEORV32_GPTMR.CTRL = tmp;
|
||||
NEORV32_GPTMR->CTRL = tmp;
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -87,7 +87,7 @@ void neorv32_gptmr_setup(int prsc, int mode, uint32_t threshold) {
|
|||
**************************************************************************/
|
||||
void neorv32_gptmr_disable(void) {
|
||||
|
||||
NEORV32_GPTMR.CTRL &= ~((uint32_t)(1 << GPTMR_CTRL_EN));
|
||||
NEORV32_GPTMR->CTRL &= ~((uint32_t)(1 << GPTMR_CTRL_EN));
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -96,7 +96,7 @@ void neorv32_gptmr_disable(void) {
|
|||
**************************************************************************/
|
||||
void neorv32_gptmr_enable(void) {
|
||||
|
||||
NEORV32_GPTMR.CTRL |= ((uint32_t)(1 << GPTMR_CTRL_EN));
|
||||
NEORV32_GPTMR->CTRL |= ((uint32_t)(1 << GPTMR_CTRL_EN));
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -105,5 +105,5 @@ void neorv32_gptmr_enable(void) {
|
|||
**************************************************************************/
|
||||
void neorv32_gptmr_restart(void) {
|
||||
|
||||
NEORV32_GPTMR.COUNT = 0;
|
||||
NEORV32_GPTMR->COUNT = 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -76,9 +76,9 @@ void neorv32_mtime_set_time(uint64_t time) {
|
|||
|
||||
cycles.uint64 = time;
|
||||
|
||||
NEORV32_MTIME.TIME_LO = 0;
|
||||
NEORV32_MTIME.TIME_HI = cycles.uint32[1];
|
||||
NEORV32_MTIME.TIME_LO = cycles.uint32[0];
|
||||
NEORV32_MTIME->TIME_LO = 0;
|
||||
NEORV32_MTIME->TIME_HI = cycles.uint32[1];
|
||||
NEORV32_MTIME->TIME_LO = cycles.uint32[0];
|
||||
|
||||
asm volatile("nop"); // delay due to write buffer
|
||||
}
|
||||
|
|
@ -100,9 +100,9 @@ uint64_t neorv32_mtime_get_time(void) {
|
|||
|
||||
uint32_t tmp1, tmp2, tmp3;
|
||||
while(1) {
|
||||
tmp1 = NEORV32_MTIME.TIME_HI;
|
||||
tmp2 = NEORV32_MTIME.TIME_LO;
|
||||
tmp3 = NEORV32_MTIME.TIME_HI;
|
||||
tmp1 = NEORV32_MTIME->TIME_HI;
|
||||
tmp2 = NEORV32_MTIME->TIME_LO;
|
||||
tmp3 = NEORV32_MTIME->TIME_HI;
|
||||
if (tmp1 == tmp3) {
|
||||
break;
|
||||
}
|
||||
|
|
@ -132,9 +132,9 @@ void neorv32_mtime_set_timecmp(uint64_t timecmp) {
|
|||
|
||||
cycles.uint64 = timecmp;
|
||||
|
||||
NEORV32_MTIME.TIMECMP_LO = -1; // prevent MTIMECMP from temporarily becoming smaller than the lesser of the old and new values
|
||||
NEORV32_MTIME.TIMECMP_HI = cycles.uint32[1];
|
||||
NEORV32_MTIME.TIMECMP_LO = cycles.uint32[0];
|
||||
NEORV32_MTIME->TIMECMP_LO = -1; // prevent MTIMECMP from temporarily becoming smaller than the lesser of the old and new values
|
||||
NEORV32_MTIME->TIMECMP_HI = cycles.uint32[1];
|
||||
NEORV32_MTIME->TIMECMP_LO = cycles.uint32[0];
|
||||
|
||||
asm volatile("nop"); // delay due to write buffer
|
||||
}
|
||||
|
|
@ -152,8 +152,8 @@ uint64_t neorv32_mtime_get_timecmp(void) {
|
|||
uint32_t uint32[sizeof(uint64_t)/sizeof(uint32_t)];
|
||||
} cycles;
|
||||
|
||||
cycles.uint32[0] = NEORV32_MTIME.TIMECMP_LO;
|
||||
cycles.uint32[1] = NEORV32_MTIME.TIMECMP_HI;
|
||||
cycles.uint32[0] = NEORV32_MTIME->TIMECMP_LO;
|
||||
cycles.uint32[1] = NEORV32_MTIME->TIMECMP_HI;
|
||||
|
||||
return cycles.uint64;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -71,7 +71,7 @@ int neorv32_neoled_available(void) {
|
|||
**************************************************************************/
|
||||
void neorv32_neoled_setup(uint32_t prsc, uint32_t t_total, uint32_t t_high_zero, uint32_t t_high_one) {
|
||||
|
||||
NEORV32_NEOLED.CTRL = 0; // reset
|
||||
NEORV32_NEOLED->CTRL = 0; // reset
|
||||
|
||||
// module enable
|
||||
uint32_t ct_enable = 1 << NEOLED_CTRL_EN;
|
||||
|
|
@ -89,7 +89,7 @@ void neorv32_neoled_setup(uint32_t prsc, uint32_t t_total, uint32_t t_high_zero,
|
|||
uint32_t ct_t_one = (t_high_one & 0x1f) << NEOLED_CTRL_T_ONE_H_0;
|
||||
|
||||
// set new configuration
|
||||
NEORV32_NEOLED.CTRL = ct_enable | ct_prsc | ct_t_total | ct_t_zero | ct_t_one;
|
||||
NEORV32_NEOLED->CTRL = ct_enable | ct_prsc | ct_t_total | ct_t_zero | ct_t_one;
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -161,10 +161,10 @@ void neorv32_neoled_setup_ws2812(void) {
|
|||
**************************************************************************/
|
||||
void neorv32_neoled_set_mode(uint32_t mode) {
|
||||
|
||||
uint32_t ctrl = NEORV32_NEOLED.CTRL;
|
||||
uint32_t ctrl = NEORV32_NEOLED->CTRL;
|
||||
ctrl &= ~(0b1 << NEOLED_CTRL_MODE); // clear current mode
|
||||
ctrl |= ((mode & 1) << NEOLED_CTRL_MODE); // set new mode
|
||||
NEORV32_NEOLED.CTRL = ctrl;
|
||||
NEORV32_NEOLED->CTRL = ctrl;
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -174,7 +174,7 @@ void neorv32_neoled_set_mode(uint32_t mode) {
|
|||
void neorv32_neoled_strobe_blocking(void) {
|
||||
|
||||
while(1) { // wait for FIFO full flag to clear
|
||||
if ((NEORV32_NEOLED.CTRL & (1 << NEOLED_CTRL_TX_FULL)) == 0) {
|
||||
if ((NEORV32_NEOLED->CTRL & (1 << NEOLED_CTRL_TX_FULL)) == 0) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
|
@ -189,11 +189,11 @@ void neorv32_neoled_strobe_blocking(void) {
|
|||
void neorv32_neoled_strobe_nonblocking(void) {
|
||||
|
||||
const uint32_t mask = 1 << NEOLED_CTRL_STROBE; // strobe bit
|
||||
uint32_t ctrl = NEORV32_NEOLED.CTRL;
|
||||
uint32_t ctrl = NEORV32_NEOLED->CTRL;
|
||||
|
||||
NEORV32_NEOLED.CTRL = ctrl | mask; // set strobe bit
|
||||
NEORV32_NEOLED.DATA = 0; // send any data to trigger strobe command
|
||||
NEORV32_NEOLED.CTRL = ctrl & (~mask); // clear strobe bit
|
||||
NEORV32_NEOLED->CTRL = ctrl | mask; // set strobe bit
|
||||
NEORV32_NEOLED->DATA = 0; // send any data to trigger strobe command
|
||||
NEORV32_NEOLED->CTRL = ctrl & (~mask); // clear strobe bit
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -202,7 +202,7 @@ void neorv32_neoled_strobe_nonblocking(void) {
|
|||
**************************************************************************/
|
||||
void neorv32_neoled_enable(void) {
|
||||
|
||||
NEORV32_NEOLED.CTRL |= ((uint32_t)(1 << NEOLED_CTRL_EN));
|
||||
NEORV32_NEOLED->CTRL |= ((uint32_t)(1 << NEOLED_CTRL_EN));
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -211,7 +211,7 @@ void neorv32_neoled_enable(void) {
|
|||
**************************************************************************/
|
||||
void neorv32_neoled_disable(void) {
|
||||
|
||||
NEORV32_NEOLED.CTRL &= ~((uint32_t)(1 << NEOLED_CTRL_EN));
|
||||
NEORV32_NEOLED->CTRL &= ~((uint32_t)(1 << NEOLED_CTRL_EN));
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -225,7 +225,7 @@ void neorv32_neoled_disable(void) {
|
|||
void neorv32_neoled_write_blocking(uint32_t data) {
|
||||
|
||||
while(1) { // wait for FIFO full flag to clear
|
||||
if ((NEORV32_NEOLED.CTRL & (1 << NEOLED_CTRL_TX_FULL)) == 0) {
|
||||
if ((NEORV32_NEOLED->CTRL & (1 << NEOLED_CTRL_TX_FULL)) == 0) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
|
@ -241,7 +241,7 @@ void neorv32_neoled_write_blocking(uint32_t data) {
|
|||
**************************************************************************/
|
||||
uint32_t neorv32_neoled_get_buffer_size(void) {
|
||||
|
||||
uint32_t tmp = NEORV32_NEOLED.CTRL;
|
||||
uint32_t tmp = NEORV32_NEOLED->CTRL;
|
||||
tmp = tmp >> NEOLED_CTRL_BUFS_0;
|
||||
tmp = tmp & 0xf; // isolate buffer size bits
|
||||
|
||||
|
|
|
|||
|
|
@ -69,8 +69,8 @@ int neorv32_onewire_available(void) {
|
|||
int neorv32_onewire_setup(uint32_t t_base) {
|
||||
|
||||
// reset
|
||||
NEORV32_ONEWIRE.CTRL = 0;
|
||||
NEORV32_ONEWIRE.DATA = 0;
|
||||
NEORV32_ONEWIRE->CTRL = 0;
|
||||
NEORV32_ONEWIRE->DATA = 0;
|
||||
|
||||
const uint32_t PRSC_LUT[4] = {2, 4, 8, 64}; // subset of system clock prescalers
|
||||
|
||||
|
|
@ -101,7 +101,7 @@ int neorv32_onewire_setup(uint32_t t_base) {
|
|||
ctrl |= 1 << ONEWIRE_CTRL_EN; // module enable
|
||||
ctrl |= (clk_prsc_sel & 0x3) << ONEWIRE_CTRL_PRSC0; // clock prescaler
|
||||
ctrl |= ((clkdiv - 1) & 0xff) << ONEWIRE_CTRL_CLKDIV0; // clock divider
|
||||
NEORV32_ONEWIRE.CTRL = ctrl;
|
||||
NEORV32_ONEWIRE->CTRL = ctrl;
|
||||
|
||||
return (int)((t_clock_x250ps / 4) * PRSC_LUT[clk_prsc_sel] * clkdiv);
|
||||
}
|
||||
|
|
@ -112,7 +112,7 @@ int neorv32_onewire_setup(uint32_t t_base) {
|
|||
**************************************************************************/
|
||||
void neorv32_onewire_enable(void) {
|
||||
|
||||
NEORV32_ONEWIRE.CTRL |= (1 << ONEWIRE_CTRL_EN);
|
||||
NEORV32_ONEWIRE->CTRL |= (1 << ONEWIRE_CTRL_EN);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -121,7 +121,7 @@ void neorv32_onewire_enable(void) {
|
|||
**************************************************************************/
|
||||
void neorv32_onewire_disable(void) {
|
||||
|
||||
NEORV32_ONEWIRE.CTRL &= ~(1 << ONEWIRE_CTRL_EN);
|
||||
NEORV32_ONEWIRE->CTRL &= ~(1 << ONEWIRE_CTRL_EN);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -132,7 +132,7 @@ void neorv32_onewire_disable(void) {
|
|||
**************************************************************************/
|
||||
int neorv32_onewire_sense(void) {
|
||||
|
||||
if (NEORV32_ONEWIRE.CTRL & (1 << ONEWIRE_CTRL_SENSE)) {
|
||||
if (NEORV32_ONEWIRE->CTRL & (1 << ONEWIRE_CTRL_SENSE)) {
|
||||
return 1;
|
||||
}
|
||||
else {
|
||||
|
|
@ -156,7 +156,7 @@ int neorv32_onewire_sense(void) {
|
|||
int neorv32_onewire_busy(void) {
|
||||
|
||||
// check busy flag
|
||||
if (NEORV32_ONEWIRE.CTRL & (1 << ONEWIRE_CTRL_BUSY)) {
|
||||
if (NEORV32_ONEWIRE->CTRL & (1 << ONEWIRE_CTRL_BUSY)) {
|
||||
return 1;
|
||||
}
|
||||
else {
|
||||
|
|
@ -173,7 +173,7 @@ int neorv32_onewire_busy(void) {
|
|||
void neorv32_onewire_reset(void) {
|
||||
|
||||
// trigger reset-pulse operation
|
||||
NEORV32_ONEWIRE.CTRL |= 1 << ONEWIRE_CTRL_TRIG_RST;
|
||||
NEORV32_ONEWIRE->CTRL |= 1 << ONEWIRE_CTRL_TRIG_RST;
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -187,7 +187,7 @@ void neorv32_onewire_reset(void) {
|
|||
int neorv32_onewire_reset_get_presence(void) {
|
||||
|
||||
// check presence bit
|
||||
if (NEORV32_ONEWIRE.CTRL & (1 << ONEWIRE_CTRL_PRESENCE)) {
|
||||
if (NEORV32_ONEWIRE->CTRL & (1 << ONEWIRE_CTRL_PRESENCE)) {
|
||||
return 0;
|
||||
}
|
||||
else {
|
||||
|
|
@ -204,10 +204,10 @@ int neorv32_onewire_reset_get_presence(void) {
|
|||
void neorv32_onewire_read_bit(void) {
|
||||
|
||||
// output all-one
|
||||
NEORV32_ONEWIRE.DATA = 0xff;
|
||||
NEORV32_ONEWIRE->DATA = 0xff;
|
||||
|
||||
// trigger bit operation
|
||||
NEORV32_ONEWIRE.CTRL |= (1 << ONEWIRE_CTRL_TRIG_BIT);
|
||||
NEORV32_ONEWIRE->CTRL |= (1 << ONEWIRE_CTRL_TRIG_BIT);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -221,7 +221,7 @@ void neorv32_onewire_read_bit(void) {
|
|||
uint8_t neorv32_onewire_read_bit_get(void) {
|
||||
|
||||
// return read bit
|
||||
if (NEORV32_ONEWIRE.DATA & (1 << 7)) { // LSB first -> read bit is in MSB
|
||||
if (NEORV32_ONEWIRE->DATA & (1 << 7)) { // LSB first -> read bit is in MSB
|
||||
return 1;
|
||||
}
|
||||
else {
|
||||
|
|
@ -241,14 +241,14 @@ void neorv32_onewire_write_bit(uint8_t bit) {
|
|||
|
||||
// set replicated bit
|
||||
if (bit) {
|
||||
NEORV32_ONEWIRE.DATA = 0xff;
|
||||
NEORV32_ONEWIRE->DATA = 0xff;
|
||||
}
|
||||
else {
|
||||
NEORV32_ONEWIRE.DATA = 0x00;
|
||||
NEORV32_ONEWIRE->DATA = 0x00;
|
||||
}
|
||||
|
||||
// trigger bit operation
|
||||
NEORV32_ONEWIRE.CTRL |= (1 << ONEWIRE_CTRL_TRIG_BIT);
|
||||
NEORV32_ONEWIRE->CTRL |= (1 << ONEWIRE_CTRL_TRIG_BIT);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -260,10 +260,10 @@ void neorv32_onewire_write_bit(uint8_t bit) {
|
|||
void neorv32_onewire_read_byte(void) {
|
||||
|
||||
// output all-one
|
||||
NEORV32_ONEWIRE.DATA = 0xff;
|
||||
NEORV32_ONEWIRE->DATA = 0xff;
|
||||
|
||||
//trigger byte operation
|
||||
NEORV32_ONEWIRE.CTRL |= (1 << ONEWIRE_CTRL_TRIG_BYTE);
|
||||
NEORV32_ONEWIRE->CTRL |= (1 << ONEWIRE_CTRL_TRIG_BYTE);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -277,7 +277,7 @@ void neorv32_onewire_read_byte(void) {
|
|||
uint8_t neorv32_onewire_read_byte_get(void) {
|
||||
|
||||
// return read bit
|
||||
return (uint8_t)(NEORV32_ONEWIRE.DATA);
|
||||
return (uint8_t)(NEORV32_ONEWIRE->DATA);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -291,10 +291,10 @@ uint8_t neorv32_onewire_read_byte_get(void) {
|
|||
void neorv32_onewire_write_byte(uint8_t byte) {
|
||||
|
||||
// TX data
|
||||
NEORV32_ONEWIRE.DATA = (uint32_t)byte;
|
||||
NEORV32_ONEWIRE->DATA = (uint32_t)byte;
|
||||
|
||||
// and trigger byte operation
|
||||
NEORV32_ONEWIRE.CTRL |= (1 << ONEWIRE_CTRL_TRIG_BYTE);
|
||||
NEORV32_ONEWIRE->CTRL |= (1 << ONEWIRE_CTRL_TRIG_BYTE);
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -68,7 +68,7 @@ int neorv32_pwm_available(void) {
|
|||
**************************************************************************/
|
||||
void neorv32_pwm_setup(int prsc) {
|
||||
|
||||
NEORV32_PWM.CTRL = 0; // reset
|
||||
NEORV32_PWM->CTRL = 0; // reset
|
||||
|
||||
uint32_t ct_enable = 1;
|
||||
ct_enable = ct_enable << PWM_CTRL_EN;
|
||||
|
|
@ -76,7 +76,7 @@ void neorv32_pwm_setup(int prsc) {
|
|||
uint32_t ct_prsc = (uint32_t)(prsc & 0x07);
|
||||
ct_prsc = ct_prsc << PWM_CTRL_PRSC0;
|
||||
|
||||
NEORV32_PWM.CTRL = ct_enable | ct_prsc;
|
||||
NEORV32_PWM->CTRL = ct_enable | ct_prsc;
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -85,7 +85,7 @@ void neorv32_pwm_setup(int prsc) {
|
|||
**************************************************************************/
|
||||
void neorv32_pwm_disable(void) {
|
||||
|
||||
NEORV32_PWM.CTRL &= ~((uint32_t)(1 << PWM_CTRL_EN));
|
||||
NEORV32_PWM->CTRL &= ~((uint32_t)(1 << PWM_CTRL_EN));
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -94,7 +94,7 @@ void neorv32_pwm_disable(void) {
|
|||
**************************************************************************/
|
||||
void neorv32_pwm_enable(void) {
|
||||
|
||||
NEORV32_PWM.CTRL |= ((uint32_t)(1 << PWM_CTRL_EN));
|
||||
NEORV32_PWM->CTRL |= ((uint32_t)(1 << PWM_CTRL_EN));
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -135,12 +135,12 @@ void neorv32_pwm_set(int channel, uint8_t dc) {
|
|||
const uint32_t dc_mask = 0xff;
|
||||
uint32_t dc_new = (uint32_t)dc;
|
||||
|
||||
uint32_t tmp = NEORV32_PWM.DC[channel/4];
|
||||
uint32_t tmp = NEORV32_PWM->DC[channel/4];
|
||||
|
||||
tmp &= ~(dc_mask << ((channel % 4) * 8)); // clear previous duty cycle
|
||||
tmp |= dc_new << ((channel % 4) * 8); // set new duty cycle
|
||||
|
||||
NEORV32_PWM.DC[channel/4] = tmp;
|
||||
NEORV32_PWM->DC[channel/4] = tmp;
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -156,7 +156,7 @@ uint8_t neorv32_pwm_get(int channel) {
|
|||
return 0; // out of range
|
||||
}
|
||||
|
||||
uint32_t rd = NEORV32_PWM.DC[channel/4] >> (((channel % 4) * 8));
|
||||
uint32_t rd = NEORV32_PWM->DC[channel/4] >> (((channel % 4) * 8));
|
||||
|
||||
return (uint8_t)rd;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -74,7 +74,7 @@ void neorv32_rte_setup(void) {
|
|||
neorv32_cpu_csr_write(CSR_MIP, 0);
|
||||
|
||||
// clear BUSKEEPER error flags
|
||||
NEORV32_BUSKEEPER.CTRL = 0;
|
||||
NEORV32_BUSKEEPER->CTRL = 0;
|
||||
|
||||
// install debug handler for all trap sources
|
||||
uint8_t id;
|
||||
|
|
@ -245,7 +245,7 @@ static void __neorv32_rte_debug_handler(void) {
|
|||
}
|
||||
// check specific cause if bus access fault exception
|
||||
else if ((trap_cause == TRAP_CODE_I_ACCESS) || (trap_cause == TRAP_CODE_L_ACCESS) || (trap_cause == TRAP_CODE_S_ACCESS)) {
|
||||
uint32_t bus_err = NEORV32_BUSKEEPER.CTRL;
|
||||
uint32_t bus_err = NEORV32_BUSKEEPER->CTRL;
|
||||
if (bus_err & (1<<BUSKEEPER_ERR_FLAG)) { // exception caused by bus system?
|
||||
if (bus_err & (1<<BUSKEEPER_ERR_TYPE)) {
|
||||
neorv32_uart0_puts(" [TIMEOUT_ERR]");
|
||||
|
|
|
|||
|
|
@ -68,13 +68,13 @@ int neorv32_sdi_available(void) {
|
|||
**************************************************************************/
|
||||
void neorv32_sdi_setup(uint32_t irq_mask) {
|
||||
|
||||
NEORV32_SDI.CTRL = 0; // reset
|
||||
NEORV32_SDI->CTRL = 0; // reset
|
||||
|
||||
uint32_t tmp = 0;
|
||||
tmp |= (uint32_t)(1 & 0x01) << SDI_CTRL_EN;
|
||||
tmp |= (uint32_t)(irq_mask & (0x0f << SDI_CTRL_IRQ_RX_AVAIL));
|
||||
|
||||
NEORV32_SDI.CTRL = tmp;
|
||||
NEORV32_SDI->CTRL = tmp;
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -83,7 +83,7 @@ void neorv32_sdi_setup(uint32_t irq_mask) {
|
|||
**************************************************************************/
|
||||
void neorv32_sdi_rx_clear(void) {
|
||||
|
||||
NEORV32_SDI.CTRL |= (uint32_t)(1 << SDI_CTRL_CLR_RX);
|
||||
NEORV32_SDI->CTRL |= (uint32_t)(1 << SDI_CTRL_CLR_RX);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -92,7 +92,7 @@ void neorv32_sdi_rx_clear(void) {
|
|||
**************************************************************************/
|
||||
void neorv32_sdi_disable(void) {
|
||||
|
||||
NEORV32_SDI.CTRL &= ~((uint32_t)(1 << SDI_CTRL_EN));
|
||||
NEORV32_SDI->CTRL &= ~((uint32_t)(1 << SDI_CTRL_EN));
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -101,7 +101,7 @@ void neorv32_sdi_disable(void) {
|
|||
**************************************************************************/
|
||||
void neorv32_sdi_enable(void) {
|
||||
|
||||
NEORV32_SDI.CTRL |= ((uint32_t)(1 << SDI_CTRL_EN));
|
||||
NEORV32_SDI->CTRL |= ((uint32_t)(1 << SDI_CTRL_EN));
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -112,7 +112,7 @@ void neorv32_sdi_enable(void) {
|
|||
**************************************************************************/
|
||||
int neorv32_sdi_get_fifo_depth(void) {
|
||||
|
||||
uint32_t tmp = (NEORV32_SDI.CTRL >> SDI_CTRL_FIFO_LSB) & 0x0f;
|
||||
uint32_t tmp = (NEORV32_SDI->CTRL >> SDI_CTRL_FIFO_LSB) & 0x0f;
|
||||
return (int)(1 << tmp);
|
||||
}
|
||||
|
||||
|
|
@ -125,11 +125,11 @@ int neorv32_sdi_get_fifo_depth(void) {
|
|||
**************************************************************************/
|
||||
int neorv32_sdi_put(uint8_t data) {
|
||||
|
||||
if (NEORV32_SDI.CTRL & (1 << SDI_CTRL_TX_FULL)) {
|
||||
if (NEORV32_SDI->CTRL & (1 << SDI_CTRL_TX_FULL)) {
|
||||
return -1;
|
||||
}
|
||||
else {
|
||||
NEORV32_SDI.DATA = (uint32_t)data;
|
||||
NEORV32_SDI->DATA = (uint32_t)data;
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
|
@ -142,7 +142,7 @@ int neorv32_sdi_put(uint8_t data) {
|
|||
**************************************************************************/
|
||||
void neorv32_sdi_put_nonblocking(uint8_t data) {
|
||||
|
||||
NEORV32_SDI.DATA = (uint32_t)data;
|
||||
NEORV32_SDI->DATA = (uint32_t)data;
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -154,8 +154,8 @@ void neorv32_sdi_put_nonblocking(uint8_t data) {
|
|||
**************************************************************************/
|
||||
int neorv32_sdi_get(uint8_t* data) {
|
||||
|
||||
if (NEORV32_SDI.CTRL & (1 << SDI_CTRL_RX_AVAIL)) {
|
||||
*data = (uint8_t)NEORV32_SDI.DATA;
|
||||
if (NEORV32_SDI->CTRL & (1 << SDI_CTRL_RX_AVAIL)) {
|
||||
*data = (uint8_t)NEORV32_SDI->DATA;
|
||||
return 0;
|
||||
}
|
||||
else {
|
||||
|
|
@ -171,5 +171,5 @@ int neorv32_sdi_get(uint8_t* data) {
|
|||
**************************************************************************/
|
||||
uint8_t neorv32_sdi_get_nonblocking(void) {
|
||||
|
||||
return (uint8_t)NEORV32_SDI.DATA;
|
||||
return (uint8_t)NEORV32_SDI->DATA;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -72,7 +72,7 @@ int neorv32_spi_available(void) {
|
|||
**************************************************************************/
|
||||
void neorv32_spi_setup(int prsc, int cdiv, int clk_phase, int clk_polarity, int data_size, int irq_config) {
|
||||
|
||||
NEORV32_SPI.CTRL = 0; // reset
|
||||
NEORV32_SPI->CTRL = 0; // reset
|
||||
|
||||
uint32_t tmp = 0;
|
||||
tmp |= (uint32_t)(1 & 0x01) << SPI_CTRL_EN;
|
||||
|
|
@ -83,7 +83,7 @@ void neorv32_spi_setup(int prsc, int cdiv, int clk_phase, int clk_polarity, int
|
|||
tmp |= (uint32_t)(cdiv & 0x0f) << SPI_CTRL_CDIV0;
|
||||
tmp |= (uint32_t)(irq_config & 0x03) << SPI_CTRL_IRQ0;
|
||||
|
||||
NEORV32_SPI.CTRL = tmp;
|
||||
NEORV32_SPI->CTRL = tmp;
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -96,7 +96,7 @@ uint32_t neorv32_spi_get_clock_speed(void) {
|
|||
|
||||
const uint32_t PRSC_LUT[8] = {2, 4, 8, 64, 128, 1024, 2048, 4096};
|
||||
|
||||
uint32_t ctrl = NEORV32_SPI.CTRL;
|
||||
uint32_t ctrl = NEORV32_SPI->CTRL;
|
||||
uint32_t prsc_sel = (ctrl >> SPI_CTRL_PRSC0) & 0x7;
|
||||
uint32_t clock_div = (ctrl >> SPI_CTRL_CDIV0) & 0xf;
|
||||
|
||||
|
|
@ -110,7 +110,7 @@ uint32_t neorv32_spi_get_clock_speed(void) {
|
|||
**************************************************************************/
|
||||
void neorv32_spi_disable(void) {
|
||||
|
||||
NEORV32_SPI.CTRL &= ~((uint32_t)(1 << SPI_CTRL_EN));
|
||||
NEORV32_SPI->CTRL &= ~((uint32_t)(1 << SPI_CTRL_EN));
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -119,7 +119,7 @@ void neorv32_spi_disable(void) {
|
|||
**************************************************************************/
|
||||
void neorv32_spi_enable(void) {
|
||||
|
||||
NEORV32_SPI.CTRL |= ((uint32_t)(1 << SPI_CTRL_EN));
|
||||
NEORV32_SPI->CTRL |= ((uint32_t)(1 << SPI_CTRL_EN));
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -130,7 +130,7 @@ void neorv32_spi_enable(void) {
|
|||
**************************************************************************/
|
||||
int neorv32_spi_get_fifo_depth(void) {
|
||||
|
||||
uint32_t tmp = (NEORV32_SPI.CTRL >> SPI_CTRL_FIFO_LSB) & 0x0f;
|
||||
uint32_t tmp = (NEORV32_SPI->CTRL >> SPI_CTRL_FIFO_LSB) & 0x0f;
|
||||
return (int)(1 << tmp);
|
||||
}
|
||||
|
||||
|
|
@ -144,10 +144,10 @@ int neorv32_spi_get_fifo_depth(void) {
|
|||
**************************************************************************/
|
||||
void neorv32_spi_cs_en(int cs) {
|
||||
|
||||
uint32_t tmp = NEORV32_SPI.CTRL;
|
||||
uint32_t tmp = NEORV32_SPI->CTRL;
|
||||
tmp &= ~(0xf << SPI_CTRL_CS_SEL0); // clear old configuration
|
||||
tmp |= (1 << SPI_CTRL_CS_EN) | ((cs & 7) << SPI_CTRL_CS_SEL0); // set new configuration
|
||||
NEORV32_SPI.CTRL = tmp;
|
||||
NEORV32_SPI->CTRL = tmp;
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -157,7 +157,7 @@ void neorv32_spi_cs_en(int cs) {
|
|||
* @note The SPI chip select output lines are HIGH when deactivated.
|
||||
**************************************************************************/
|
||||
void neorv32_spi_cs_dis(void) {
|
||||
NEORV32_SPI.CTRL &= ~(1 << SPI_CTRL_CS_EN);
|
||||
NEORV32_SPI->CTRL &= ~(1 << SPI_CTRL_CS_EN);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -171,10 +171,10 @@ void neorv32_spi_cs_dis(void) {
|
|||
**************************************************************************/
|
||||
uint32_t neorv32_spi_trans(uint32_t tx_data) {
|
||||
|
||||
NEORV32_SPI.DATA = tx_data; // trigger transfer
|
||||
while((NEORV32_SPI.CTRL & (1<<SPI_CTRL_BUSY)) != 0); // wait for current transfer to finish
|
||||
NEORV32_SPI->DATA = tx_data; // trigger transfer
|
||||
while((NEORV32_SPI->CTRL & (1<<SPI_CTRL_BUSY)) != 0); // wait for current transfer to finish
|
||||
|
||||
return NEORV32_SPI.DATA;
|
||||
return NEORV32_SPI->DATA;
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -185,7 +185,7 @@ uint32_t neorv32_spi_trans(uint32_t tx_data) {
|
|||
**************************************************************************/
|
||||
void neorv32_spi_put_nonblocking(uint32_t tx_data) {
|
||||
|
||||
NEORV32_SPI.DATA = tx_data; // trigger transfer
|
||||
NEORV32_SPI->DATA = tx_data; // trigger transfer
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -196,7 +196,7 @@ void neorv32_spi_put_nonblocking(uint32_t tx_data) {
|
|||
**************************************************************************/
|
||||
uint32_t neorv32_spi_get_nonblocking(void) {
|
||||
|
||||
return NEORV32_SPI.DATA;
|
||||
return NEORV32_SPI->DATA;
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -207,7 +207,7 @@ uint32_t neorv32_spi_get_nonblocking(void) {
|
|||
**************************************************************************/
|
||||
int neorv32_spi_busy(void) {
|
||||
|
||||
if ((NEORV32_SPI.CTRL & (1<<SPI_CTRL_BUSY)) != 0) {
|
||||
if ((NEORV32_SPI->CTRL & (1<<SPI_CTRL_BUSY)) != 0) {
|
||||
return 1;
|
||||
}
|
||||
else {
|
||||
|
|
|
|||
|
|
@ -68,14 +68,14 @@ void neorv32_trng_enable(void) {
|
|||
|
||||
int i;
|
||||
|
||||
NEORV32_TRNG.CTRL = 0; // reset
|
||||
NEORV32_TRNG->CTRL = 0; // reset
|
||||
|
||||
// wait for all internal components to reset
|
||||
for (i=0; i<512; i++) {
|
||||
asm volatile ("nop");
|
||||
}
|
||||
|
||||
NEORV32_TRNG.CTRL = 1 << TRNG_CTRL_EN; // activate
|
||||
NEORV32_TRNG->CTRL = 1 << TRNG_CTRL_EN; // activate
|
||||
|
||||
// "warm-up"
|
||||
for (i=0; i<512; i++) {
|
||||
|
|
@ -92,7 +92,7 @@ void neorv32_trng_enable(void) {
|
|||
**************************************************************************/
|
||||
void neorv32_trng_disable(void) {
|
||||
|
||||
NEORV32_TRNG.CTRL = 0;
|
||||
NEORV32_TRNG->CTRL = 0;
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -101,7 +101,7 @@ void neorv32_trng_disable(void) {
|
|||
**************************************************************************/
|
||||
void neorv32_trng_fifo_clear(void) {
|
||||
|
||||
NEORV32_TRNG.CTRL |= 1 << TRNG_CTRL_FIFO_CLR; // bit auto clears
|
||||
NEORV32_TRNG->CTRL |= 1 << TRNG_CTRL_FIFO_CLR; // bit auto clears
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -113,7 +113,7 @@ void neorv32_trng_fifo_clear(void) {
|
|||
**************************************************************************/
|
||||
int neorv32_trng_get(uint8_t *data) {
|
||||
|
||||
uint32_t tmp = NEORV32_TRNG.CTRL;
|
||||
uint32_t tmp = NEORV32_TRNG->CTRL;
|
||||
*data = (uint8_t)(tmp >> TRNG_CTRL_DATA_LSB);
|
||||
|
||||
if (tmp & (1<<TRNG_CTRL_VALID)) { // output data valid?
|
||||
|
|
@ -134,7 +134,7 @@ int neorv32_trng_get(uint8_t *data) {
|
|||
**************************************************************************/
|
||||
int neorv32_trng_check_sim_mode(void) {
|
||||
|
||||
if (NEORV32_TRNG.CTRL & (1<<TRNG_CTRL_SIM_MODE)) {
|
||||
if (NEORV32_TRNG->CTRL & (1<<TRNG_CTRL_SIM_MODE)) {
|
||||
return -1; // simulation mode (PRNG)
|
||||
}
|
||||
else {
|
||||
|
|
|
|||
|
|
@ -69,14 +69,14 @@ int neorv32_twi_available(void) {
|
|||
**************************************************************************/
|
||||
void neorv32_twi_setup(int prsc, int cdiv, int csen) {
|
||||
|
||||
NEORV32_TWI.CTRL = 0; // reset
|
||||
NEORV32_TWI->CTRL = 0; // reset
|
||||
|
||||
uint32_t ctrl = 0;
|
||||
ctrl |= ((uint32_t)( 1) << TWI_CTRL_EN);
|
||||
ctrl |= ((uint32_t)(prsc & 0x07) << TWI_CTRL_PRSC0);
|
||||
ctrl |= ((uint32_t)(cdiv & 0x0F) << TWI_CTRL_CDIV0);
|
||||
ctrl |= ((uint32_t)(csen & 0x01) << TWI_CTRL_CSEN);
|
||||
NEORV32_TWI.CTRL = ctrl;
|
||||
NEORV32_TWI->CTRL = ctrl;
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -85,7 +85,7 @@ void neorv32_twi_setup(int prsc, int cdiv, int csen) {
|
|||
**************************************************************************/
|
||||
void neorv32_twi_disable(void) {
|
||||
|
||||
NEORV32_TWI.CTRL &= ~((uint32_t)(1 << TWI_CTRL_EN));
|
||||
NEORV32_TWI->CTRL &= ~((uint32_t)(1 << TWI_CTRL_EN));
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -94,7 +94,7 @@ void neorv32_twi_disable(void) {
|
|||
**************************************************************************/
|
||||
void neorv32_twi_enable(void) {
|
||||
|
||||
NEORV32_TWI.CTRL |= (uint32_t)(1 << TWI_CTRL_EN);
|
||||
NEORV32_TWI->CTRL |= (uint32_t)(1 << TWI_CTRL_EN);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -103,7 +103,7 @@ void neorv32_twi_enable(void) {
|
|||
**************************************************************************/
|
||||
void neorv32_twi_mack_enable(void) {
|
||||
|
||||
NEORV32_TWI.CTRL |= ((uint32_t)(1 << TWI_CTRL_MACK));
|
||||
NEORV32_TWI->CTRL |= ((uint32_t)(1 << TWI_CTRL_MACK));
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -112,7 +112,7 @@ void neorv32_twi_mack_enable(void) {
|
|||
**************************************************************************/
|
||||
void neorv32_twi_mack_disable(void) {
|
||||
|
||||
NEORV32_TWI.CTRL &= ~((uint32_t)(1 << TWI_CTRL_MACK));
|
||||
NEORV32_TWI->CTRL &= ~((uint32_t)(1 << TWI_CTRL_MACK));
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -123,7 +123,7 @@ void neorv32_twi_mack_disable(void) {
|
|||
**************************************************************************/
|
||||
int neorv32_twi_busy(void) {
|
||||
|
||||
if (NEORV32_TWI.CTRL & (1 << TWI_CTRL_BUSY)) {
|
||||
if (NEORV32_TWI->CTRL & (1 << TWI_CTRL_BUSY)) {
|
||||
return 1;
|
||||
}
|
||||
else {
|
||||
|
|
@ -158,11 +158,11 @@ int neorv32_twi_start_trans(uint8_t a) {
|
|||
**************************************************************************/
|
||||
int neorv32_twi_trans(uint8_t d) {
|
||||
|
||||
NEORV32_TWI.DATA = (uint32_t)d; // send data
|
||||
while (NEORV32_TWI.CTRL & (1 << TWI_CTRL_BUSY)); // wait until idle again
|
||||
NEORV32_TWI->DATA = (uint32_t)d; // send data
|
||||
while (NEORV32_TWI->CTRL & (1 << TWI_CTRL_BUSY)); // wait until idle again
|
||||
|
||||
// check for ACK/NACK
|
||||
if (NEORV32_TWI.CTRL & (1 << TWI_CTRL_ACK)) {
|
||||
if (NEORV32_TWI->CTRL & (1 << TWI_CTRL_ACK)) {
|
||||
return 0; // ACK received
|
||||
}
|
||||
else {
|
||||
|
|
@ -178,7 +178,7 @@ int neorv32_twi_trans(uint8_t d) {
|
|||
**************************************************************************/
|
||||
uint8_t neorv32_twi_get_data(void) {
|
||||
|
||||
return (uint8_t)NEORV32_TWI.DATA; // get RX data from previous transmission
|
||||
return (uint8_t)NEORV32_TWI->DATA; // get RX data from previous transmission
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -189,8 +189,8 @@ uint8_t neorv32_twi_get_data(void) {
|
|||
**************************************************************************/
|
||||
void neorv32_twi_generate_stop(void) {
|
||||
|
||||
NEORV32_TWI.CTRL |= (uint32_t)(1 << TWI_CTRL_STOP); // generate STOP condition
|
||||
while (NEORV32_TWI.CTRL & (1 << TWI_CTRL_BUSY)); // wait until idle again
|
||||
NEORV32_TWI->CTRL |= (uint32_t)(1 << TWI_CTRL_STOP); // generate STOP condition
|
||||
while (NEORV32_TWI->CTRL & (1 << TWI_CTRL_BUSY)); // wait until idle again
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -201,8 +201,8 @@ void neorv32_twi_generate_stop(void) {
|
|||
**************************************************************************/
|
||||
void neorv32_twi_generate_start(void) {
|
||||
|
||||
NEORV32_TWI.CTRL |= (1 << TWI_CTRL_START); // generate START condition
|
||||
while (NEORV32_TWI.CTRL & (1 << TWI_CTRL_BUSY)); // wait until idle again
|
||||
NEORV32_TWI->CTRL |= (1 << TWI_CTRL_START); // generate START condition
|
||||
while (NEORV32_TWI->CTRL & (1 << TWI_CTRL_BUSY)); // wait until idle again
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -213,7 +213,7 @@ void neorv32_twi_generate_start(void) {
|
|||
**************************************************************************/
|
||||
int neorv32_twi_bus_claimed(void) {
|
||||
|
||||
if (NEORV32_TWI.CTRL & (1 << TWI_CTRL_CLAIMED)) {
|
||||
if (NEORV32_TWI->CTRL & (1 << TWI_CTRL_CLAIMED)) {
|
||||
return 1;
|
||||
}
|
||||
else {
|
||||
|
|
|
|||
|
|
@ -73,7 +73,7 @@ int neorv32_wdt_available(void) {
|
|||
**************************************************************************/
|
||||
void neorv32_wdt_setup(uint32_t timeout, int lock, int debug_en, int sleep_en) {
|
||||
|
||||
NEORV32_WDT.CTRL = 0; // reset and disable
|
||||
NEORV32_WDT->CTRL = 0; // reset and disable
|
||||
|
||||
uint32_t enable_int = ((uint32_t)(1)) << WDT_CTRL_EN;
|
||||
uint32_t timeout_int = ((uint32_t)(timeout & 0xffffffU)) << WDT_CTRL_TIMEOUT_LSB;
|
||||
|
|
@ -81,11 +81,11 @@ void neorv32_wdt_setup(uint32_t timeout, int lock, int debug_en, int sleep_en) {
|
|||
uint32_t sleep_en_int = ((uint32_t)(sleep_en & 0x1U)) << WDT_CTRL_SEN;
|
||||
|
||||
// update WDT control register
|
||||
NEORV32_WDT.CTRL = enable_int | timeout_int | debug_en_int | sleep_en_int;
|
||||
NEORV32_WDT->CTRL = enable_int | timeout_int | debug_en_int | sleep_en_int;
|
||||
|
||||
// lock configuration?
|
||||
if (lock) {
|
||||
NEORV32_WDT.CTRL |= 1 << WDT_CTRL_LOCK;
|
||||
NEORV32_WDT->CTRL |= 1 << WDT_CTRL_LOCK;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -99,10 +99,10 @@ int neorv32_wdt_disable(void) {
|
|||
|
||||
const uint32_t en_mask_c = (uint32_t)(1 << WDT_CTRL_EN);
|
||||
|
||||
NEORV32_WDT.CTRL &= en_mask_c; // try to disable
|
||||
NEORV32_WDT->CTRL &= en_mask_c; // try to disable
|
||||
|
||||
// check if WDT is really off
|
||||
if (NEORV32_WDT.CTRL & en_mask_c) {
|
||||
if (NEORV32_WDT->CTRL & en_mask_c) {
|
||||
return -1; // still active
|
||||
}
|
||||
else {
|
||||
|
|
@ -116,7 +116,7 @@ int neorv32_wdt_disable(void) {
|
|||
**************************************************************************/
|
||||
void neorv32_wdt_feed(void) {
|
||||
|
||||
NEORV32_WDT.CTRL |= (uint32_t)(1 << WDT_CTRL_RESET);
|
||||
NEORV32_WDT->CTRL |= (uint32_t)(1 << WDT_CTRL_RESET);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -127,7 +127,7 @@ void neorv32_wdt_feed(void) {
|
|||
**************************************************************************/
|
||||
int neorv32_wdt_get_cause(void) {
|
||||
|
||||
if (NEORV32_WDT.CTRL & (1 << WDT_CTRL_RCAUSE)) { // reset caused by watchdog
|
||||
if (NEORV32_WDT->CTRL & (1 << WDT_CTRL_RCAUSE)) { // reset caused by watchdog
|
||||
return 1;
|
||||
}
|
||||
else { // reset caused by system (external or OCD)
|
||||
|
|
|
|||
|
|
@ -80,11 +80,11 @@ int neorv32_xip_setup(uint8_t prsc, uint8_t cpol, uint8_t cpha, uint8_t rd_cmd)
|
|||
}
|
||||
|
||||
// reset and disable module
|
||||
NEORV32_XIP.CTRL = 0;
|
||||
NEORV32_XIP->CTRL = 0;
|
||||
|
||||
// clear data registers
|
||||
NEORV32_XIP.DATA_LO = 0;
|
||||
NEORV32_XIP.DATA_HI = 0; // will not trigger SPI transfer since module is disabled
|
||||
NEORV32_XIP->DATA_LO = 0;
|
||||
NEORV32_XIP->DATA_HI = 0; // will not trigger SPI transfer since module is disabled
|
||||
|
||||
uint32_t ctrl = 0;
|
||||
ctrl |= ((uint32_t)(1 )) << XIP_CTRL_EN; // enable module
|
||||
|
|
@ -94,16 +94,16 @@ int neorv32_xip_setup(uint8_t prsc, uint8_t cpol, uint8_t cpha, uint8_t rd_cmd)
|
|||
ctrl |= ((uint32_t)(8 )) << XIP_CTRL_SPI_NBYTES_LSB; // set 8 bytes transfer size as default
|
||||
ctrl |= ((uint32_t)(rd_cmd & 0xff)) << XIP_CTRL_RD_CMD_LSB;
|
||||
|
||||
NEORV32_XIP.CTRL = ctrl;
|
||||
NEORV32_XIP->CTRL = ctrl;
|
||||
|
||||
// send 64 SPI dummy clocks but without an active CS
|
||||
NEORV32_XIP.DATA_LO = 0;
|
||||
NEORV32_XIP.DATA_HI = 0; // trigger SPI transfer
|
||||
NEORV32_XIP->DATA_LO = 0;
|
||||
NEORV32_XIP->DATA_HI = 0; // trigger SPI transfer
|
||||
|
||||
// wait for transfer to complete
|
||||
while (NEORV32_XIP.CTRL & (1 << XIP_CTRL_PHY_BUSY)); // direct SPI mode -> check PHY status
|
||||
while (NEORV32_XIP->CTRL & (1 << XIP_CTRL_PHY_BUSY)); // direct SPI mode -> check PHY status
|
||||
|
||||
NEORV32_XIP.CTRL |= 1 << XIP_CTRL_SPI_CSEN; // finally enable automatic SPI chip-select
|
||||
NEORV32_XIP->CTRL |= 1 << XIP_CTRL_SPI_CSEN; // finally enable automatic SPI chip-select
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -127,7 +127,7 @@ int neorv32_xip_start(uint8_t abytes, uint32_t page_base) {
|
|||
}
|
||||
page_base >>= 28;
|
||||
|
||||
uint32_t ctrl = NEORV32_XIP.CTRL;
|
||||
uint32_t ctrl = NEORV32_XIP->CTRL;
|
||||
|
||||
// address bytes send to SPI flash
|
||||
ctrl &= ~(3 << XIP_CTRL_XIP_ABYTES_LSB); // clear old configuration
|
||||
|
|
@ -144,7 +144,7 @@ int neorv32_xip_start(uint8_t abytes, uint32_t page_base) {
|
|||
|
||||
ctrl |= 1 << XIP_CTRL_XIP_EN; // enable XIP mode
|
||||
|
||||
NEORV32_XIP.CTRL = ctrl;
|
||||
NEORV32_XIP->CTRL = ctrl;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -157,7 +157,7 @@ int neorv32_xip_start(uint8_t abytes, uint32_t page_base) {
|
|||
**************************************************************************/
|
||||
void neorv32_xip_highspeed_enable(void) {
|
||||
|
||||
NEORV32_XIP.CTRL |= 1 << XIP_CTRL_HIGHSPEED;
|
||||
NEORV32_XIP->CTRL |= 1 << XIP_CTRL_HIGHSPEED;
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -166,7 +166,7 @@ void neorv32_xip_highspeed_enable(void) {
|
|||
**************************************************************************/
|
||||
void neorv32_xip_highspeed_disable(void) {
|
||||
|
||||
NEORV32_XIP.CTRL &= ~(1 << XIP_CTRL_HIGHSPEED);
|
||||
NEORV32_XIP->CTRL &= ~(1 << XIP_CTRL_HIGHSPEED);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -177,7 +177,7 @@ void neorv32_xip_highspeed_disable(void) {
|
|||
**************************************************************************/
|
||||
void neorv32_xip_burst_mode_enable(void) {
|
||||
|
||||
NEORV32_XIP.CTRL |= 1 << XIP_CTRL_BURST_EN;
|
||||
NEORV32_XIP->CTRL |= 1 << XIP_CTRL_BURST_EN;
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -186,7 +186,7 @@ void neorv32_xip_burst_mode_enable(void) {
|
|||
**************************************************************************/
|
||||
void neorv32_xip_burst_mode_disable(void) {
|
||||
|
||||
NEORV32_XIP.CTRL &= ~(1 << XIP_CTRL_BURST_EN);
|
||||
NEORV32_XIP->CTRL &= ~(1 << XIP_CTRL_BURST_EN);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -207,10 +207,10 @@ int neorv32_xip_spi_trans(uint8_t nbytes, uint64_t *rtx_data) {
|
|||
}
|
||||
|
||||
// configure number of bytes to transfer
|
||||
uint32_t ctrl = NEORV32_XIP.CTRL;
|
||||
uint32_t ctrl = NEORV32_XIP->CTRL;
|
||||
ctrl &= ~(0xF << XIP_CTRL_SPI_NBYTES_LSB); // clear old configuration
|
||||
ctrl |= nbytes << XIP_CTRL_SPI_NBYTES_LSB; // set new configuration
|
||||
NEORV32_XIP.CTRL = ctrl;
|
||||
NEORV32_XIP->CTRL = ctrl;
|
||||
|
||||
union {
|
||||
uint64_t uint64;
|
||||
|
|
@ -218,13 +218,13 @@ int neorv32_xip_spi_trans(uint8_t nbytes, uint64_t *rtx_data) {
|
|||
} data;
|
||||
|
||||
data.uint64 = *rtx_data;
|
||||
NEORV32_XIP.DATA_LO = data.uint32[0];
|
||||
NEORV32_XIP.DATA_HI = data.uint32[1]; // trigger SPI transfer
|
||||
NEORV32_XIP->DATA_LO = data.uint32[0];
|
||||
NEORV32_XIP->DATA_HI = data.uint32[1]; // trigger SPI transfer
|
||||
|
||||
// wait for transfer to complete
|
||||
while (NEORV32_XIP.CTRL & (1 << XIP_CTRL_PHY_BUSY)); // direct SPI mode -> check PHY status
|
||||
while (NEORV32_XIP->CTRL & (1 << XIP_CTRL_PHY_BUSY)); // direct SPI mode -> check PHY status
|
||||
|
||||
data.uint32[0] = NEORV32_XIP.DATA_LO; // RX data is always 32-bit and LSB-aligned
|
||||
data.uint32[0] = NEORV32_XIP->DATA_LO; // RX data is always 32-bit and LSB-aligned
|
||||
data.uint32[1] = 0;
|
||||
*rtx_data = data.uint64;
|
||||
|
||||
|
|
|
|||
|
|
@ -77,9 +77,9 @@ int neorv32_xirq_available(void) {
|
|||
**************************************************************************/
|
||||
int neorv32_xirq_setup(void) {
|
||||
|
||||
NEORV32_XIRQ.IER = 0; // disable all input channels
|
||||
NEORV32_XIRQ.IPR = 0; // clear all pending IRQs
|
||||
NEORV32_XIRQ.SCR = 0; // acknowledge (clear) XIRQ interrupt
|
||||
NEORV32_XIRQ->IER = 0; // disable all input channels
|
||||
NEORV32_XIRQ->IPR = 0; // clear all pending IRQs
|
||||
NEORV32_XIRQ->SCR = 0; // acknowledge (clear) XIRQ interrupt
|
||||
|
||||
int i;
|
||||
for (i=0; i<32; i++) {
|
||||
|
|
@ -124,8 +124,8 @@ int neorv32_xirq_get_num(void) {
|
|||
if (neorv32_xirq_available()) {
|
||||
|
||||
neorv32_cpu_csr_clr(CSR_MIE, 1 << XIRQ_FIRQ_ENABLE); // make sure XIRQ cannot fire
|
||||
NEORV32_XIRQ.IER = 0xffffffff; // try to set all enable flags
|
||||
enable = NEORV32_XIRQ.IER; // read back actually set flags
|
||||
NEORV32_XIRQ->IER = 0xffffffff; // try to set all enable flags
|
||||
enable = NEORV32_XIRQ->IER; // read back actually set flags
|
||||
|
||||
// count set bits in enable
|
||||
cnt = 0;
|
||||
|
|
@ -151,7 +151,7 @@ int neorv32_xirq_get_num(void) {
|
|||
void neorv32_xirq_clear_pending(uint8_t ch) {
|
||||
|
||||
if (ch < 32) { // channel valid?
|
||||
NEORV32_XIRQ.IPR = ~(1 << ch);
|
||||
NEORV32_XIRQ->IPR = ~(1 << ch);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -164,7 +164,7 @@ void neorv32_xirq_clear_pending(uint8_t ch) {
|
|||
void neorv32_xirq_channel_enable(uint8_t ch) {
|
||||
|
||||
if (ch < 32) { // channel valid?
|
||||
NEORV32_XIRQ.IER |= 1 << ch;
|
||||
NEORV32_XIRQ->IER |= 1 << ch;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -177,7 +177,7 @@ void neorv32_xirq_channel_enable(uint8_t ch) {
|
|||
void neorv32_xirq_channel_disable(uint8_t ch) {
|
||||
|
||||
if (ch < 32) { // channel valid?
|
||||
NEORV32_XIRQ.IER &= ~(1 << ch);
|
||||
NEORV32_XIRQ->IER &= ~(1 << ch);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -197,8 +197,8 @@ int neorv32_xirq_install(uint8_t ch, void (*handler)(void)) {
|
|||
if (ch < 32) {
|
||||
__neorv32_xirq_vector_lut[ch] = (uint32_t)handler; // install handler
|
||||
uint32_t mask = 1 << ch;
|
||||
NEORV32_XIRQ.IPR = ~mask; // clear if pending
|
||||
NEORV32_XIRQ.IER |= mask; // enable channel
|
||||
NEORV32_XIRQ->IPR = ~mask; // clear if pending
|
||||
NEORV32_XIRQ->IER |= mask; // enable channel
|
||||
return 0;
|
||||
}
|
||||
return 1;
|
||||
|
|
@ -219,8 +219,8 @@ int neorv32_xirq_uninstall(uint8_t ch) {
|
|||
if (ch < 32) {
|
||||
__neorv32_xirq_vector_lut[ch] = (uint32_t)(&__neorv32_xirq_dummy_handler); // override using dummy handler
|
||||
uint32_t mask = 1 << ch;
|
||||
NEORV32_XIRQ.IER &= ~mask; // disable channel
|
||||
NEORV32_XIRQ.IPR = ~mask; // clear if pending
|
||||
NEORV32_XIRQ->IER &= ~mask; // disable channel
|
||||
NEORV32_XIRQ->IPR = ~mask; // clear if pending
|
||||
return 0;
|
||||
}
|
||||
return 1;
|
||||
|
|
@ -235,7 +235,7 @@ static void __neorv32_xirq_core(void) {
|
|||
|
||||
neorv32_cpu_csr_write(CSR_MIP, ~(1 << XIRQ_FIRQ_PENDING)); // acknowledge XIRQ FIRQ
|
||||
|
||||
uint32_t src = NEORV32_XIRQ.SCR; // get IRQ source (with highest priority)
|
||||
uint32_t src = NEORV32_XIRQ->SCR; // get IRQ source (with highest priority)
|
||||
|
||||
// execute handler
|
||||
uint32_t xirq_handler = __neorv32_xirq_vector_lut[src];
|
||||
|
|
@ -244,8 +244,8 @@ static void __neorv32_xirq_core(void) {
|
|||
(*handler_pnt)();
|
||||
|
||||
uint32_t mask = 1 << src;
|
||||
NEORV32_XIRQ.IPR = ~mask; // clear current pending interrupt
|
||||
NEORV32_XIRQ.SCR = 0; // acknowledge current XIRQ interrupt
|
||||
NEORV32_XIRQ->IPR = ~mask; // clear current pending interrupt
|
||||
NEORV32_XIRQ->SCR = 0; // acknowledge current XIRQ interrupt
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue