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🚀 preparing release v1.11.3
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stnolting 2025-04-21 11:16:16 +02:00
parent 43467f256f
commit 2c0b0e75a9
4 changed files with 4 additions and 3 deletions
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1
CHANGELOG.md
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@ -29,6 +29,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
| Date | Version | Comment | Ticket |
|:----:|:-------:|:--------|:------:|
| 21.04.2025 | [**:rocket:1.11.3**](https://github.com/stnolting/neorv32/releases/tag/v1.11.3) | **New release** | |
| 18.04.2025 | 1.11.2.9 | adjust TWI timing to allow for repeated-start at higher TWI clock speeds | [#1237](https://github.com/stnolting/neorv32/pull/1237) |
| 18.04.2025 | 1.11.2.8 | :bug: fix bug in PMP logic: multiple signal assignments when NAPOT-mode is disabled | [#1236](https://github.com/stnolting/neorv32/pull/1236) |
| 12.04.2025 | 1.11.2.7 | :sparkles: add PWM polarity configuration | [#1230](https://github.com/stnolting/neorv32/pull/1230) |

2
docs/attrs.adoc
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@ -2,7 +2,7 @@
:email: stnolting@gmail.com
:keywords: neorv32, risc-v, riscv, rv32, fpga, soft-core, vhdl, microcontroller, cpu, soc, processor, gcc, openocd, gdb, verilog, rtl, asip, asic
:description: A size-optimized, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
:revnumber: v1.11.2
:revnumber: v1.11.3
:icons: font
:source-highlighter: highlight.js
:imagesdir: ../figures

2
rtl/core/neorv32_package.vhd
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@ -29,7 +29,7 @@ package neorv32_package is
-- Architecture Constants -----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01110209"; -- hardware version
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01110300"; -- hardware version
constant archid_c : natural := 19; -- official RISC-V architecture ID
constant XLEN : natural := 32; -- native data path width

2
sw/svd/neorv32.svd
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@ -4,7 +4,7 @@
<vendor>stnolting</vendor>
<name>neorv32</name>
<series>RISC-V</series>
<version>1.11.2</version>
<version>1.11.3</version>
<description>The NEORV32 RISC-V Processor</description>
<!-- CPU core -->