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move tri-state drivers out of core

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ONEWIRE and TWI
This commit is contained in:
stnolting 2023-03-09 19:47:27 +01:00
parent eff033bf56
commit 2c25612175
8 changed files with 105 additions and 56 deletions
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4
rtl/core/neorv32_onewire.vhd
View file

@ -12,7 +12,7 @@
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
-- # Copyright (c) 2023, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
@ -260,7 +260,7 @@ begin
begin
if rising_edge(clk_i) then
-- input synchronizer --
serial.wire_in <= serial.wire_in(0) & onewire_i; -- synchronize to prevent metastability
serial.wire_in <= serial.wire_in(0) & to_stdulogic(to_bit(onewire_i)); -- "to_bit" to avoid hardware-vs-simulation mismatch
-- bus control --
if (serial.busy = '0') or (serial.wire_hi = '1') then -- disabled/idle or active tristate request

11
rtl/core/neorv32_package.vhd
View file

@ -65,7 +65,7 @@ package neorv32_package is
-- Architecture Constants (do not modify!) ------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01080109"; -- NEORV32 version
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01080110"; -- NEORV32 version
constant archid_c : natural := 19; -- official RISC-V architecture ID
-- Check if we're inside the Matrix -------------------------------------------------------
@ -1099,10 +1099,13 @@ package neorv32_package is
sdi_dat_i : in std_ulogic := 'U'; -- controller data in, peripheral data out
sdi_csn_i : in std_ulogic := 'H'; -- chip-select
-- TWI (available if IO_TWI_EN = true) --
twi_sda_io : inout std_logic; -- twi serial data line
twi_scl_io : inout std_logic; -- twi serial clock line
twi_sda_i : in std_ulogic := 'H'; -- serial data line sense input
twi_sda_o : out std_ulogic; -- serial data line output (pull low only)
twi_scl_i : in std_ulogic := 'H'; -- serial clock line sense input
twi_scl_o : out std_ulogic; -- serial clock line output (pull low only)
-- 1-Wire Interface (available if IO_ONEWIRE_EN = true) --
onewire_io : inout std_logic; -- 1-wire bus
onewire_i : in std_ulogic := 'H'; -- 1-wire bus sense input
onewire_o : out std_ulogic; -- 1-wire bus output (pull low only)
-- PWM (available if IO_PWM_NUM_CH > 0) --
pwm_o : out std_ulogic_vector(11 downto 0); -- pwm channels
-- Custom Functions Subsystem IO --

34
rtl/core/neorv32_top.vhd
View file

@ -200,11 +200,14 @@ entity neorv32_top is
sdi_csn_i : in std_ulogic := 'H'; -- chip-select
-- TWI (available if IO_TWI_EN = true) --
twi_sda_io : inout std_logic; -- twi serial data line
twi_scl_io : inout std_logic; -- twi serial clock line
twi_sda_i : in std_ulogic := 'H'; -- serial data line sense input
twi_sda_o : out std_ulogic; -- serial data line output (pull low only)
twi_scl_i : in std_ulogic := 'H'; -- serial clock line sense input
twi_scl_o : out std_ulogic; -- serial clock line output (pull low only)
-- 1-Wire Interface (available if IO_ONEWIRE_EN = true) --
onewire_io : inout std_logic; -- 1-wire bus
onewire_i : in std_ulogic := 'H'; -- 1-wire bus sense input
onewire_o : out std_ulogic; -- 1-wire bus output (pull low only)
-- PWM (available if IO_PWM_NUM_CH > 0) --
pwm_o : out std_ulogic_vector(11 downto 0); -- pwm channels
@ -362,11 +365,6 @@ architecture neorv32_top_rtl of neorv32_top is
signal gptmr_irq : std_ulogic;
signal onewire_irq : std_ulogic;
-- tri-state drivers --
signal twi_sda_i, twi_sda_o : std_ulogic;
signal twi_scl_i, twi_scl_o : std_ulogic;
signal onewire_i, onewire_o : std_ulogic;
-- misc --
signal ext_timeout : std_ulogic;
signal ext_access : std_ulogic;
@ -1343,22 +1341,16 @@ begin
irq_o => twi_irq -- transfer done IRQ
);
resp_bus(RESP_TWI).err <= '0'; -- no access error possible
-- tri-state drivers --
twi_sda_io <= '0' when (twi_sda_o = '0') else 'Z'; -- module can only pull the line low actively
twi_scl_io <= '0' when (twi_scl_o = '0') else 'Z';
twi_sda_i <= to_stdulogic(to_bit(twi_sda_io)); -- "to_bit" to avoid hardware-vs-simulation mismatch
twi_scl_i <= to_stdulogic(to_bit(twi_scl_io));
end generate;
neorv32_twi_inst_false:
if (IO_TWI_EN = false) generate
resp_bus(RESP_TWI) <= resp_bus_entry_terminate_c;
--
twi_sda_io <= 'Z';
twi_scl_io <= 'Z';
twi_cg_en <= '0';
twi_irq <= '0';
twi_sda_o <= '1';
twi_scl_o <= '1';
twi_cg_en <= '0';
twi_irq <= '0';
end generate;
@ -1559,17 +1551,13 @@ begin
irq_o => onewire_irq -- transfer done IRQ
);
resp_bus(RESP_ONEWIRE).err <= '0'; -- no access error possible
-- tri-state driver --
onewire_io <= '0' when (onewire_o = '0') else 'Z'; -- module can only pull the line low actively
onewire_i <= to_stdulogic(to_bit(onewire_io)); -- "to_bit" to avoid hardware-vs-simulation mismatch
end generate;
neorv32_onewire_inst_false:
if (IO_ONEWIRE_EN = false) generate
resp_bus(RESP_ONEWIRE) <= resp_bus_entry_terminate_c;
--
onewire_io <= 'Z';
onewire_o <= '1';
onewire_cg_en <= '0';
onewire_irq <= '0';
end generate;

10
rtl/core/neorv32_twi.vhd
View file

@ -8,7 +8,7 @@
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
-- # Copyright (c) 2023, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
@ -380,10 +380,10 @@ begin
-- Tri-State Driver Interface -------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
twi_sda_o <= io_con.sda_out; -- NOTE: signal lines can only be actively driven low
twi_scl_o <= io_con.scl_out;
io_con.sda_in <= twi_sda_i;
io_con.scl_in <= twi_scl_i;
twi_sda_o <= io_con.sda_out; -- NOTE: signal lines can only be actively driven low
twi_scl_o <= io_con.scl_out;
io_con.sda_in <= to_stdulogic(to_bit(twi_sda_i)); -- "to_bit" to avoid hardware-vs-simulation mismatch
io_con.scl_in <= to_stdulogic(to_bit(twi_scl_i)); -- "to_bit" to avoid hardware-vs-simulation mismatch
end neorv32_twi_rtl;

18
rtl/system_integration/neorv32_SystemTop_AvalonMM.vhd
View file

@ -179,11 +179,14 @@ entity neorv32_top_avalonmm is
spi_csn_o : out std_ulogic_vector(07 downto 0); -- chip-select
-- TWI (available if IO_TWI_EN = true) --
twi_sda_io : inout std_logic := 'U'; -- twi serial data line
twi_scl_io : inout std_logic := 'U'; -- twi serial clock line
twi_sda_i : in std_ulogic := 'H'; -- serial data line sense input
twi_sda_o : out std_ulogic; -- serial data line output (pull low only)
twi_scl_i : in std_ulogic := 'H'; -- serial clock line sense input
twi_scl_o : out std_ulogic; -- serial clock line output (pull low only)
-- 1-Wire Interface (available if IO_ONEWIRE_EN = true) --
onewire_io : inout std_logic; -- 1-wire bus
onewire_i : in std_ulogic := 'H'; -- 1-wire bus sense input
onewire_o : out std_ulogic; -- 1-wire bus output (pull low only)
-- PWM (available if IO_PWM_NUM_CH > 0) --
pwm_o : out std_ulogic_vector(11 downto 0); -- pwm channels
@ -369,11 +372,14 @@ begin
spi_csn_o => spi_csn_o,
-- TWI (available if IO_TWI_EN = true) --
twi_sda_io => twi_sda_io,
twi_scl_io => twi_scl_io,
twi_sda_i => twi_sda_i,
twi_sda_o => twi_sda_o,
twi_scl_i => twi_scl_i,
twi_scl_o => twi_scl_o,
-- 1-Wire Interface (available if IO_ONEWIRE_EN = true) --
onewire_io => onewire_io,
onewire_i => onewire_i,
onewire_o => onewire_o,
-- PWM (available if IO_PWM_NUM_CH > 0) --
pwm_o => pwm_o,

34
rtl/system_integration/neorv32_SystemTop_axi4lite.vhd
View file

@ -183,10 +183,13 @@ entity neorv32_SystemTop_axi4lite is
spi_dat_i : in std_logic := '0'; -- controller data in, peripheral data out
spi_csn_o : out std_logic_vector(07 downto 0); -- SPI CS
-- TWI (available if IO_TWI_EN = true) --
twi_sda_io : inout std_logic; -- twi serial data line
twi_scl_io : inout std_logic; -- twi serial clock line
twi_sda_i : in std_ulogic := 'H'; -- serial data line sense input
twi_sda_o : out std_ulogic; -- serial data line output (pull low only)
twi_scl_i : in std_ulogic := 'H'; -- serial clock line sense input
twi_scl_o : out std_ulogic; -- serial clock line output (pull low only)
-- 1-Wire Interface (available if IO_ONEWIRE_EN = true) --
onewire_io : inout std_logic; -- 1-wire bus
onewire_i : in std_ulogic := 'H'; -- 1-wire bus sense input
onewire_o : out std_ulogic; -- 1-wire bus output (pull low only)
-- PWM (available if IO_PWM_NUM_CH > 0) --
pwm_o : out std_logic_vector(11 downto 0); -- pwm channels
-- Custom Functions Subsystem IO (available if IO_CFS_EN = true) --
@ -249,6 +252,14 @@ architecture neorv32_SystemTop_axi4lite_rtl of neorv32_SystemTop_axi4lite is
--
signal neoled_o_int : std_ulogic;
--
signal twi_sda_i_int : std_ulogic;
signal twi_sda_o_int : std_ulogic;
signal twi_scl_i_int : std_ulogic;
signal twi_scl_o_int : std_ulogic;
--
signal onewire_i_int : std_ulogic;
signal onewire_o_int : std_ulogic;
--
signal xirq_i_int : std_ulogic_vector(31 downto 0);
--
signal msw_irq_i_int : std_ulogic;
@ -412,10 +423,13 @@ begin
spi_dat_i => spi_dat_i_int, -- controller data in, peripheral data out
spi_csn_o => spi_csn_o_int, -- SPI CS
-- TWI (available if IO_TWI_EN = true) --
twi_sda_io => twi_sda_io, -- twi serial data line
twi_scl_io => twi_scl_io, -- twi serial clock line
twi_sda_i => twi_sda_i_int, -- serial data line sense input
twi_sda_o => twi_sda_o_int, -- serial data line output (pull low only)
twi_scl_i => twi_scl_i_int, -- serial clock line sense input
twi_scl_o => twi_scl_o_int, -- serial clock line output (pull low only)
-- 1-Wire Interface (available if IO_ONEWIRE_EN = true) --
onewire_io => onewire_io, -- 1-wire bus
onewire_i => onewire_i_int, -- 1-wire bus sense input
onewire_o => onewire_o_int, -- 1-wire bus output (pull low only)
-- PWM available if IO_PWM_NUM_CH > 0) --
pwm_o => pwm_o_int, -- pwm channels
-- Custom Functions Subsystem IO (available if IO_CFS_EN = true) --
@ -467,6 +481,14 @@ begin
neoled_o <= std_logic(neoled_o_int);
twi_sda_i_int <= std_ulogic(twi_sda_i);
twi_sda_o <= std_logic(twi_sda_o_int);
twi_scl_i_int <= std_ulogic(twi_scl_i);
twi_scl_o <= std_logic(twi_scl_o_int);
onewire_i_int <= std_ulogic(onewire_i);
onewire_o <= std_logic(onewire_o_int);
xirq_i_int <= std_ulogic_vector(xirq_i);
msw_irq_i_int <= std_ulogic(msw_irq_i);

25
sim/neorv32_tb.vhd
View file

@ -110,9 +110,11 @@ architecture neorv32_tb_rtl of neorv32_tb is
-- twi --
signal twi_scl, twi_sda : std_logic;
signal twi_scl_i, twi_scl_o, twi_sda_i, twi_sda_o : std_ulogic;
-- 1-wire --
signal one_wire : std_logic;
signal onewire : std_logic;
signal onewire_i, onewire_o : std_ulogic;
-- spi & sdi --
signal spi_csn: std_ulogic_vector(7 downto 0);
@ -344,10 +346,13 @@ begin
sdi_dat_i => sdi_di, -- controller data in, peripheral data out
sdi_csn_i => sdi_csn, -- chip-select
-- TWI (available if IO_TWI_EN = true) --
twi_sda_io => twi_sda, -- twi serial data line
twi_scl_io => twi_scl, -- twi serial clock line
twi_sda_i => twi_sda_i, -- serial data line sense input
twi_sda_o => twi_sda_o, -- serial data line output (pull low only)
twi_scl_i => twi_scl_i, -- serial clock line sense input
twi_scl_o => twi_scl_o, -- serial clock line output (pull low only)
-- 1-Wire Interface (available if IO_ONEWIRE_EN = true) --
onewire_io => one_wire, -- 1-wire bus
onewire_i => onewire_i, -- 1-wire bus sense input
onewire_o => onewire_o, -- 1-wire bus output (pull low only)
-- PWM (available if IO_PWM_NUM_CH > 0) --
pwm_o => open, -- pwm channels
-- Custom Functions Subsystem IO --
@ -363,12 +368,22 @@ begin
mext_irq_i => mei_ring -- machine external interrupt
);
-- TWI tri-state driver --
twi_sda <= '0' when (twi_sda_o = '0') else 'Z'; -- module can only pull the line low actively
twi_scl <= '0' when (twi_scl_o = '0') else 'Z';
twi_sda_i <= std_ulogic(twi_sda);
twi_scl_i <= std_ulogic(twi_scl);
-- 1-Wire tri-state driver --
onewire <= '0' when (onewire_o = '0') else 'Z'; -- module can only pull the line low actively
onewire_i <= std_ulogic(onewire);
-- TWI termination (pull-ups) --
twi_scl <= 'H';
twi_sda <= 'H';
-- 1-Wire termination (pull-up) --
one_wire <= 'H';
onewire <= 'H';
-- SPI/SDI echo --
sdi_clk <= spi_clk;

25
sim/simple/neorv32_tb.simple.vhd
View file

@ -110,9 +110,11 @@ architecture neorv32_tb_simple_rtl of neorv32_tb_simple is
-- twi --
signal twi_scl, twi_sda : std_logic;
signal twi_scl_i, twi_scl_o, twi_sda_i, twi_sda_o : std_ulogic;
-- 1-wire --
signal one_wire : std_logic;
signal onewire : std_logic;
signal onewire_i, onewire_o : std_ulogic;
-- spi & sdi --
signal spi_csn: std_ulogic_vector(7 downto 0);
@ -296,10 +298,13 @@ begin
sdi_dat_i => sdi_di, -- controller data in, peripheral data out
sdi_csn_i => sdi_csn, -- chip-select
-- TWI (available if IO_TWI_EN = true) --
twi_sda_io => twi_sda, -- twi serial data line
twi_scl_io => twi_scl, -- twi serial clock line
twi_sda_i => twi_sda_i, -- serial data line sense input
twi_sda_o => twi_sda_o, -- serial data line output (pull low only)
twi_scl_i => twi_scl_i, -- serial clock line sense input
twi_scl_o => twi_scl_o, -- serial clock line output (pull low only)
-- 1-Wire Interface (available if IO_ONEWIRE_EN = true) --
onewire_io => one_wire, -- 1-wire bus
onewire_i => onewire_i, -- 1-wire bus sense input
onewire_o => onewire_o, -- 1-wire bus output (pull low only)
-- PWM (available if IO_PWM_NUM_CH > 0) --
pwm_o => open, -- pwm channels
-- Custom Functions Subsystem IO --
@ -315,12 +320,22 @@ begin
mext_irq_i => mei_ring -- machine external interrupt
);
-- TWI tri-state driver --
twi_sda <= '0' when (twi_sda_o = '0') else 'Z'; -- module can only pull the line low actively
twi_scl <= '0' when (twi_scl_o = '0') else 'Z';
twi_sda_i <= std_ulogic(twi_sda);
twi_scl_i <= std_ulogic(twi_scl);
-- 1-Wire tri-state driver --
onewire <= '0' when (onewire_o = '0') else 'Z'; -- module can only pull the line low actively
onewire_i <= std_ulogic(onewire);
-- TWI termination (pull-ups) --
twi_scl <= 'H';
twi_sda <= 'H';
-- 1-Wire termination (pull-up) --
one_wire <= 'H';
onewire <= 'H';
-- SPI/SDI echo --
sdi_clk <= spi_clk;