mirror of
https://github.com/stnolting/neorv32.git
synced 2025-06-27 17:00:49 -04:00
Rework RTE trap handler look-up-table (#1295)
This commit is contained in:
stnolting
GitHub
commit
2eae568b01
4 changed files with 100 additions and 128 deletions
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@ -126,7 +126,6 @@ void __attribute__((constructor)) neorv32_constructor() {
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int main() {
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uint32_t tmp_a, tmp_b;
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uint8_t id;
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// disable machine-mode interrupts
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neorv32_cpu_csr_clr(CSR_MSTATUS, 1 << CSR_MSTATUS_MIE);
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@ -145,10 +144,38 @@ int main() {
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// -----------------------------------------------
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neorv32_rte_setup(); // this will install a full-detailed debug handler for ALL traps
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int install_err = 0;
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// initialize ALL provided trap handler (overriding the default debug handlers)
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for (id=0; id<NEORV32_RTE_NUM_TRAPS; id++) {
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install_err += neorv32_rte_handler_install(id, global_trap_handler);
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}
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// synchronous exceptions
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install_err += neorv32_rte_handler_install(RTE_TRAP_I_ACCESS, global_trap_handler);
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install_err += neorv32_rte_handler_install(RTE_TRAP_I_ILLEGAL, global_trap_handler);
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install_err += neorv32_rte_handler_install(RTE_TRAP_I_MISALIGNED, global_trap_handler);
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install_err += neorv32_rte_handler_install(RTE_TRAP_BREAKPOINT, global_trap_handler);
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install_err += neorv32_rte_handler_install(RTE_TRAP_L_MISALIGNED, global_trap_handler);
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install_err += neorv32_rte_handler_install(RTE_TRAP_L_ACCESS, global_trap_handler);
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install_err += neorv32_rte_handler_install(RTE_TRAP_S_MISALIGNED, global_trap_handler);
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install_err += neorv32_rte_handler_install(RTE_TRAP_S_ACCESS, global_trap_handler);
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install_err += neorv32_rte_handler_install(RTE_TRAP_UENV_CALL, global_trap_handler);
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install_err += neorv32_rte_handler_install(RTE_TRAP_MENV_CALL, global_trap_handler);
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install_err += neorv32_rte_handler_install(RTE_TRAP_DOUBLE_TRAP, global_trap_handler);
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// asynchronous exceptions (interrupts)
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install_err += neorv32_rte_handler_install(RTE_TRAP_MSI, global_trap_handler);
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install_err += neorv32_rte_handler_install(RTE_TRAP_MTI, global_trap_handler);
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install_err += neorv32_rte_handler_install(RTE_TRAP_MEI, global_trap_handler);
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install_err += neorv32_rte_handler_install(RTE_TRAP_FIRQ_0, global_trap_handler);
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install_err += neorv32_rte_handler_install(RTE_TRAP_FIRQ_1, global_trap_handler);
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install_err += neorv32_rte_handler_install(RTE_TRAP_FIRQ_2, global_trap_handler);
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install_err += neorv32_rte_handler_install(RTE_TRAP_FIRQ_3, global_trap_handler);
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install_err += neorv32_rte_handler_install(RTE_TRAP_FIRQ_4, global_trap_handler);
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install_err += neorv32_rte_handler_install(RTE_TRAP_FIRQ_5, global_trap_handler);
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install_err += neorv32_rte_handler_install(RTE_TRAP_FIRQ_6, global_trap_handler);
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install_err += neorv32_rte_handler_install(RTE_TRAP_FIRQ_7, global_trap_handler);
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install_err += neorv32_rte_handler_install(RTE_TRAP_FIRQ_8, global_trap_handler);
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install_err += neorv32_rte_handler_install(RTE_TRAP_FIRQ_9, global_trap_handler);
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install_err += neorv32_rte_handler_install(RTE_TRAP_FIRQ_10, global_trap_handler);
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install_err += neorv32_rte_handler_install(RTE_TRAP_FIRQ_11, global_trap_handler);
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install_err += neorv32_rte_handler_install(RTE_TRAP_FIRQ_12, global_trap_handler);
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install_err += neorv32_rte_handler_install(RTE_TRAP_FIRQ_13, global_trap_handler);
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install_err += neorv32_rte_handler_install(RTE_TRAP_FIRQ_14, global_trap_handler);
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install_err += neorv32_rte_handler_install(RTE_TRAP_FIRQ_15, global_trap_handler);
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if (install_err) {
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PRINT_CRITICAL("RTE fail!\n");
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return 1;
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@ -1,13 +1,9 @@
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# Application makefile.
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# Use this makefile to configure all relevant CPU / compiler options.
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# Processor-check program makefile
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# Override the default CPU ISA
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# Maximum ISA configuration (but without C)
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override MARCH = rv32ima_zba_zbb_zbs_zbkb_zbkc_zbkx_zknd_zkne_zknh_zksh_zksed_zicsr_zfinx_zifencei_zicond
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# Override the default RISC-V GCC prefix
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#RISCV_PREFIX ?= riscv-none-elf-
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# Override default optimization goal
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# Optimization goal
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EFFORT = -Os
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# Add extended debug symbols
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@ -23,15 +19,11 @@ override USER_FLAGS += -Wl,--defsym,__neorv32_rom_size=32k
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override USER_FLAGS += -Wl,--defsym,__neorv32_ram_size=8k
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# Adjust maximum heap size
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override USER_FLAGS += -Wl,--defsym,__neorv32_heap_size=3096
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override USER_FLAGS += -Wl,--defsym,__neorv32_heap_size=3k
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# Simulation arguments
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override GHDL_RUN_FLAGS ?= --stop-time=15ms
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# Additional sources
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#APP_SRC += $(wildcard ./*.c)
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#APP_INC += -I .
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# Set path to NEORV32 root directory
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NEORV32_HOME ?= ../../..
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@ -20,43 +20,41 @@
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* NEORV32 runtime environment trap IDs.
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**************************************************************************/
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/**@{*/
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/**< Trap ID enumeration */
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enum NEORV32_RTE_TRAP_enum {
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// --- synchronous exceptions ---
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RTE_TRAP_I_ACCESS = 0, /**< Instruction access fault */
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RTE_TRAP_I_ILLEGAL = 1, /**< Illegal instruction */
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RTE_TRAP_I_MISALIGNED = 2, /**< Instruction address misaligned */
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RTE_TRAP_BREAKPOINT = 3, /**< Breakpoint (EBREAK instruction) */
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RTE_TRAP_L_MISALIGNED = 4, /**< Load address misaligned */
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RTE_TRAP_L_ACCESS = 5, /**< Load access fault */
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RTE_TRAP_S_MISALIGNED = 6, /**< Store address misaligned */
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RTE_TRAP_S_ACCESS = 7, /**< Store access fault */
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RTE_TRAP_UENV_CALL = 8, /**< Environment call from user mode (ECALL instruction) */
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RTE_TRAP_MENV_CALL = 9, /**< Environment call from machine mode (ECALL instruction) */
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RTE_TRAP_DOUBLE_TRAP = 10,/**< Double-trap */
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// --- asynchronous exceptions ---
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RTE_TRAP_MSI = 11, /**< Machine software interrupt */
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RTE_TRAP_MTI = 12, /**< Machine timer interrupt */
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RTE_TRAP_MEI = 13, /**< Machine external interrupt */
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RTE_TRAP_FIRQ_0 = 14, /**< Fast interrupt channel 0 */
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RTE_TRAP_FIRQ_1 = 15, /**< Fast interrupt channel 1 */
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RTE_TRAP_FIRQ_2 = 16, /**< Fast interrupt channel 2 */
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RTE_TRAP_FIRQ_3 = 17, /**< Fast interrupt channel 3 */
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RTE_TRAP_FIRQ_4 = 18, /**< Fast interrupt channel 4 */
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RTE_TRAP_FIRQ_5 = 19, /**< Fast interrupt channel 5 */
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RTE_TRAP_FIRQ_6 = 20, /**< Fast interrupt channel 6 */
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RTE_TRAP_FIRQ_7 = 21, /**< Fast interrupt channel 7 */
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RTE_TRAP_FIRQ_8 = 22, /**< Fast interrupt channel 8 */
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RTE_TRAP_FIRQ_9 = 23, /**< Fast interrupt channel 9 */
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RTE_TRAP_FIRQ_10 = 24, /**< Fast interrupt channel 10 */
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RTE_TRAP_FIRQ_11 = 25, /**< Fast interrupt channel 11 */
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RTE_TRAP_FIRQ_12 = 26, /**< Fast interrupt channel 12 */
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RTE_TRAP_FIRQ_13 = 27, /**< Fast interrupt channel 13 */
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RTE_TRAP_FIRQ_14 = 28, /**< Fast interrupt channel 14 */
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RTE_TRAP_FIRQ_15 = 29 /**< Fast interrupt channel 15 */
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};
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/**< Total number of trap IDs */
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#define NEORV32_RTE_NUM_TRAPS 30
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/**< Synchronous exceptions */
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#define RTE_TRAP_I_ACCESS TRAP_CODE_I_MISALIGNED /**< Instruction access fault */
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#define RTE_TRAP_I_ILLEGAL TRAP_CODE_I_ACCESS /**< Illegal instruction */
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#define RTE_TRAP_I_MISALIGNED TRAP_CODE_I_ILLEGAL /**< Instruction address misaligned */
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#define RTE_TRAP_BREAKPOINT TRAP_CODE_BREAKPOINT /**< Breakpoint (EBREAK instruction) */
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#define RTE_TRAP_L_MISALIGNED TRAP_CODE_L_MISALIGNED /**< Load address misaligned */
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#define RTE_TRAP_L_ACCESS TRAP_CODE_L_ACCESS /**< Load access fault */
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#define RTE_TRAP_S_MISALIGNED TRAP_CODE_S_MISALIGNED /**< Store address misaligned */
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#define RTE_TRAP_S_ACCESS TRAP_CODE_S_ACCESS /**< Store access fault */
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#define RTE_TRAP_UENV_CALL TRAP_CODE_UENV_CALL /**< Environment call from user mode (ECALL instruction) */
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#define RTE_TRAP_MENV_CALL TRAP_CODE_MENV_CALL /**< Environment call from machine mode (ECALL instruction) */
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#define RTE_TRAP_DOUBLE_TRAP TRAP_CODE_DOUBLE_TRAP /**< Double-trap */
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/**< Asynchronous exceptions */
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#define RTE_TRAP_MSI TRAP_CODE_MSI /**< Machine software interrupt */
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#define RTE_TRAP_MTI TRAP_CODE_MTI /**< Machine timer interrupt */
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#define RTE_TRAP_MEI TRAP_CODE_MEI /**< Machine external interrupt */
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#define RTE_TRAP_FIRQ_0 TRAP_CODE_FIRQ_0 /**< Fast interrupt channel 0 */
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#define RTE_TRAP_FIRQ_1 TRAP_CODE_FIRQ_1 /**< Fast interrupt channel 1 */
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#define RTE_TRAP_FIRQ_2 TRAP_CODE_FIRQ_2 /**< Fast interrupt channel 2 */
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#define RTE_TRAP_FIRQ_3 TRAP_CODE_FIRQ_3 /**< Fast interrupt channel 3 */
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#define RTE_TRAP_FIRQ_4 TRAP_CODE_FIRQ_4 /**< Fast interrupt channel 4 */
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#define RTE_TRAP_FIRQ_5 TRAP_CODE_FIRQ_5 /**< Fast interrupt channel 5 */
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#define RTE_TRAP_FIRQ_6 TRAP_CODE_FIRQ_6 /**< Fast interrupt channel 6 */
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#define RTE_TRAP_FIRQ_7 TRAP_CODE_FIRQ_7 /**< Fast interrupt channel 7 */
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#define RTE_TRAP_FIRQ_8 TRAP_CODE_FIRQ_8 /**< Fast interrupt channel 8 */
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#define RTE_TRAP_FIRQ_9 TRAP_CODE_FIRQ_9 /**< Fast interrupt channel 9 */
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#define RTE_TRAP_FIRQ_10 TRAP_CODE_FIRQ_10 /**< Fast interrupt channel 10 */
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#define RTE_TRAP_FIRQ_11 TRAP_CODE_FIRQ_11 /**< Fast interrupt channel 11 */
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#define RTE_TRAP_FIRQ_12 TRAP_CODE_FIRQ_12 /**< Fast interrupt channel 12 */
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#define RTE_TRAP_FIRQ_13 TRAP_CODE_FIRQ_13 /**< Fast interrupt channel 13 */
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#define RTE_TRAP_FIRQ_14 TRAP_CODE_FIRQ_14 /**< Fast interrupt channel 14 */
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#define RTE_TRAP_FIRQ_15 TRAP_CODE_FIRQ_15 /**< Fast interrupt channel 15 */
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/**< Total number of trap codes */
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#define NEORV32_RTE_NUM_TRAPS (2*32)
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/**@}*/
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/**********************************************************************//**
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@ -65,7 +63,7 @@ enum NEORV32_RTE_TRAP_enum {
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/**@{*/
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void neorv32_rte_setup(void);
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void neorv32_rte_core(void);
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int neorv32_rte_handler_install(int id, void (*handler)(void));
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int neorv32_rte_handler_install(uint32_t code, void (*handler)(void));
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void neorv32_rte_debug_handler(void);
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uint32_t neorv32_rte_context_get(int x);
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void neorv32_rte_context_put(int x, uint32_t data);
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@ -13,21 +13,13 @@
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#include <neorv32.h>
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// ------------------------------------------------------------------------------------------------
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// RTE private variables and functions
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// ------------------------------------------------------------------------------------------------
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// private trap vector look-up table (for all cores!)
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static volatile uint32_t __neorv32_rte_vector_lut[NEORV32_RTE_NUM_TRAPS];
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static volatile uint32_t __attribute__((aligned(4))) __neorv32_rte_vector_lut[2][32];
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// private helper functions
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static void __neorv32_rte_print_hex(uint32_t num, int digits);
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// ------------------------------------------------------------------------------------------------
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// RTE core functions
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// ------------------------------------------------------------------------------------------------
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/**********************************************************************//**
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* NEORV32 runtime environment (RTE):
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* Setup RTE.
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@ -43,8 +35,8 @@ void neorv32_rte_setup(void) {
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// clear mstatus, set previous privilege level to machine-mode
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neorv32_cpu_csr_write(CSR_MSTATUS, (1<<CSR_MSTATUS_MPP_H) | (1<<CSR_MSTATUS_MPP_L));
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// configure trap handler base address
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neorv32_cpu_csr_write(CSR_MTVEC, (uint32_t)(&neorv32_rte_core));
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// configure trap handler base address (direct mode)
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neorv32_cpu_csr_write(CSR_MTVEC, (uint32_t)(&neorv32_rte_core) & 0xfffffffcU);
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// disable all IRQ channels
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neorv32_cpu_csr_write(CSR_MIE, 0);
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@ -52,12 +44,12 @@ void neorv32_rte_setup(void) {
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// install debug handler for all trap sources (executed only on core 0)
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if (neorv32_cpu_csr_read(CSR_MHARTID) == 0) {
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int index;
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for (index = 0; index < ((int)NEORV32_RTE_NUM_TRAPS); index++) {
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__neorv32_rte_vector_lut[index] = (uint32_t)(&neorv32_rte_debug_handler);
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for (index = 0; index < 32; index++) {
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__neorv32_rte_vector_lut[0][index] = (uint32_t)(&neorv32_rte_debug_handler);
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__neorv32_rte_vector_lut[1][index] = (uint32_t)(&neorv32_rte_debug_handler);
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}
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asm volatile ("fence"); // flush handler table to main memory
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}
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asm volatile ("fence"); // flush handler table to main memory
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}
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@ -68,24 +60,22 @@ void neorv32_rte_setup(void) {
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* @note Trap handler installation applies to both cores. Hence, both
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* cores will execute the same handler for the same trap.
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*
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* @param[in] id Identifier (type) of the targeted trap
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* @param[in] code Identifier (type) of the targeted trap
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* See #NEORV32_RTE_TRAP_enum.
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*
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* @param[in] handler The actual handler function for the specified trap
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* (function MUST be of type "void function(void);").
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* (function must be of type "void function(void);").
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*
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* @return 0 if success, -1 if invalid trap ID.
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* @return 0 if success, -1 if invalid trap code.
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**************************************************************************/
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int neorv32_rte_handler_install(int id, void (*handler)(void)) {
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int neorv32_rte_handler_install(uint32_t code, void (*handler)(void)) {
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// check if invalid trap ID
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if ((uint32_t)id < NEORV32_RTE_NUM_TRAPS) {
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__neorv32_rte_vector_lut[id] = (uint32_t)handler; // install handler
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asm volatile ("fence"); // flush updated handler table to main memory
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return 0;
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if (code & (~0x8000001fU)) { // invalid trap code
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return -1;
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}
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else {
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return -1;
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__neorv32_rte_vector_lut[code >> 31][code] = (uint32_t)handler;
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return 0;
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}
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}
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@ -150,41 +140,10 @@ void __attribute__((__naked__,aligned(4))) neorv32_rte_core(void) {
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// reload trap table from main memory
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asm volatile ("fence");
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// find according trap handler base address
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// get trap handler base address
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uint32_t mcause = neorv32_cpu_csr_read(CSR_MCAUSE);
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uint32_t handler_base = 0;
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switch (neorv32_cpu_csr_read(CSR_MCAUSE)) {
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case TRAP_CODE_I_ACCESS: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_I_ACCESS]; break;
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case TRAP_CODE_I_ILLEGAL: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_I_ILLEGAL]; break;
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case TRAP_CODE_I_MISALIGNED: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_I_MISALIGNED]; break;
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case TRAP_CODE_BREAKPOINT: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_BREAKPOINT]; break;
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case TRAP_CODE_L_MISALIGNED: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_L_MISALIGNED]; break;
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case TRAP_CODE_L_ACCESS: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_L_ACCESS]; break;
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case TRAP_CODE_S_MISALIGNED: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_S_MISALIGNED]; break;
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case TRAP_CODE_S_ACCESS: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_S_ACCESS]; break;
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case TRAP_CODE_UENV_CALL: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_UENV_CALL]; break;
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case TRAP_CODE_MENV_CALL: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_MENV_CALL]; break;
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case TRAP_CODE_DOUBLE_TRAP: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_DOUBLE_TRAP]; break;
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case TRAP_CODE_MSI: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_MSI]; break;
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case TRAP_CODE_MTI: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_MTI]; break;
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case TRAP_CODE_MEI: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_MEI]; break;
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case TRAP_CODE_FIRQ_0: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_0]; break;
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case TRAP_CODE_FIRQ_1: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_1]; break;
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case TRAP_CODE_FIRQ_2: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_2]; break;
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case TRAP_CODE_FIRQ_3: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_3]; break;
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case TRAP_CODE_FIRQ_4: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_4]; break;
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case TRAP_CODE_FIRQ_5: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_5]; break;
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case TRAP_CODE_FIRQ_6: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_6]; break;
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case TRAP_CODE_FIRQ_7: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_7]; break;
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case TRAP_CODE_FIRQ_8: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_8]; break;
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case TRAP_CODE_FIRQ_9: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_9]; break;
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case TRAP_CODE_FIRQ_10: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_10]; break;
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case TRAP_CODE_FIRQ_11: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_11]; break;
|
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case TRAP_CODE_FIRQ_12: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_12]; break;
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||||
case TRAP_CODE_FIRQ_13: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_13]; break;
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||||
case TRAP_CODE_FIRQ_14: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_14]; break;
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||||
case TRAP_CODE_FIRQ_15: handler_base = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_15]; break;
|
||||
default: handler_base = (uint32_t)(&neorv32_rte_debug_handler); break;
|
||||
}
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||||
handler_base = __neorv32_rte_vector_lut[mcause >> 31][mcause & 31];
|
||||
|
||||
// call handler
|
||||
if (handler_base != 0) {
|
||||
|
|
@ -195,21 +154,20 @@ void __attribute__((__naked__,aligned(4))) neorv32_rte_core(void) {
|
|||
|
||||
// compute return address (for exceptions only)
|
||||
// do not alter return address if instruction access exception (fatal?)
|
||||
uint32_t cause = neorv32_cpu_csr_read(CSR_MCAUSE);
|
||||
if (((cause >> 31) == 0) && (cause != TRAP_CODE_I_ACCESS)) {
|
||||
if (((mcause >> 31) == 0) && (mcause != TRAP_CODE_I_ACCESS)) {
|
||||
|
||||
uint32_t rte_mepc = neorv32_cpu_csr_read(CSR_MEPC);
|
||||
rte_mepc += 4; // default: faulting instruction is uncompressed
|
||||
uint32_t mepc = neorv32_cpu_csr_read(CSR_MEPC);
|
||||
mepc += 4; // default: faulting instruction is uncompressed
|
||||
|
||||
#ifdef __riscv_c
|
||||
// adjust return address if compressed instruction
|
||||
if (neorv32_cpu_csr_read(CSR_MISA) & (1 << CSR_MISA_C)) { // C extension implemented?
|
||||
if ((neorv32_cpu_csr_read(CSR_MTINST) & 3) != 3) { // faulting instruction is compressed instruction
|
||||
rte_mepc -= 2;
|
||||
}
|
||||
if ((neorv32_cpu_csr_read(CSR_MTINST) & 3) != 3) { // faulting instruction is compressed instruction
|
||||
mepc -= 2;
|
||||
}
|
||||
#endif
|
||||
|
||||
// update return address
|
||||
neorv32_cpu_csr_write(CSR_MEPC, rte_mepc);
|
||||
neorv32_cpu_csr_write(CSR_MEPC, mepc);
|
||||
}
|
||||
|
||||
// restore context
|
||||
|
|
@ -404,10 +362,6 @@ void neorv32_rte_debug_handler(void) {
|
|||
}
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
// Private helper functions
|
||||
// ------------------------------------------------------------------------------------------------
|
||||
|
||||
/**********************************************************************//**
|
||||
* NEORV32 runtime environment (RTE):
|
||||
* Private function to print the lowest 0 to 8 hex characters of a
|
||||
|
|
@ -417,7 +371,7 @@ void neorv32_rte_debug_handler(void) {
|
|||
*
|
||||
* @param[in] digits Number of hexadecimal digits to print (0..8).
|
||||
**************************************************************************/
|
||||
void __neorv32_rte_print_hex(uint32_t num, int digits) {
|
||||
static void __neorv32_rte_print_hex(uint32_t num, int digits) {
|
||||
|
||||
int i = 0;
|
||||
const char hex_symbols[] = "0123456789ABCDEF";
|
||||
|
|
@ -432,3 +386,4 @@ void __neorv32_rte_print_hex(uint32_t num, int digits) {
|
|||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue