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[docs] minor fixes

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stnolting 2023-09-01 21:08:31 +02:00
parent 107c72ab61
commit 2fe805809e
2 changed files with 4 additions and 4 deletions
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4
README.md
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@ -71,8 +71,8 @@ not working as expected. See how to [contribute](https://github.com/stnolting/ne
[![release](https://img.shields.io/github/v/release/stnolting/neorv32?longCache=true&style=flat-square&logo=GitHub)](https://github.com/stnolting/neorv32/releases)
[![commits-since-latest-release](https://img.shields.io/github/commits-since/stnolting/neorv32/latest?longCache=true&style=flat-square&logo=GitHub)](https://github.com/stnolting/neorv32/releases)
| Task | Repository | CI Status |
|:-----|:-----------|:----------|
| Task / Subproject | Repository | CI Status |
|:------------------|:-----------|:----------|
| GitHub Pages (docs) | [neorv32](https://github.com/stnolting/neorv32) | [![GitHub Pages](https://img.shields.io/website.svg?label=stnolting.github.io%2Fneorv32&longCache=true&style=flat-square&url=http%3A%2F%2Fstnolting.github.io%2Fneorv32%2Findex.html&logo=GitHub)](https://stnolting.github.io/neorv32) |
| Build documentation | [neorv32](https://github.com/stnolting/neorv32) | [![Documentation](https://img.shields.io/github/actions/workflow/status/stnolting/neorv32/Documentation.yml?branch=main&longCache=true&style=flat-square&label=Documentation&logo=Github%20Actions&logoColor=fff)](https://github.com/stnolting/neorv32/actions?query=workflow%3ADocumentation) |
| Processor (SoC) verification | [neorv32](https://github.com/stnolting/neorv32) | [![Processor](https://img.shields.io/github/actions/workflow/status/stnolting/neorv32/Processor.yml?branch=main&longCache=true&style=flat-square&label=Processor%20Check&logo=Github%20Actions&logoColor=fff)](https://github.com/stnolting/neorv32/actions?query=workflow%3AProcessor) |

4
docs/datasheet/cpu_csr.adoc
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@ -318,8 +318,8 @@ interrupt is triggered or an exception is raised.
[IMPORTANT]
Physically, the NEORV32's `mcounteren` CSR is implemented as a **single 1-bit register**. Setting _any_ bit of
the CSR will result in all bits being set. Hence, user-mode access can only be granted for _all_ counter CSRs
or denied for _all_ counter CSRs.
the CSR will result in all bits being set. Hence, user-mode access can either be granted for **all** counter CSRs
or entirely denied allowing access to **none** counter CSRs.
{empty} +