[rtl] add legacy folder

for deprecated core modules that might still be handy for building custom processor setups

docs/datasheet/overview.adoc

@@ -140,6 +140,7 @@ neorv32               - Project home folder
 ├rtl                  - VHDL sources
 │├core                - Core sources of the CPU & SoC
 ││└mem                - SoC-internal memories (default architectures)
+│├legacy              - Deprecated/legacy HDL modules
 │├processor_templates - Pre-configured SoC wrappers
 │├system_integration  - System wrappers for advanced connectivity
 │└test_setups         - Minimal test setup "SoCs" used in the User Guide

rtl/README.md

@@ -1,34 +1,34 @@
 ## Hardware RTL Sources
 
-
 ### [`core`](https://github.com/stnolting/neorv32/tree/main/rtl/core)
 
 This folder contains the core VHDL files for the NEORV32 CPU and the NEORV32 Processor.
-When creating a new synthesis/simulation project make sure that all `*.vhd` files from this folder are added to a
-*new design library* called `neorv32`.
+When creating a new synthesis/simulation project make sure that all `*.vhd` files from this
+folder are added to a **new design library** called `neorv32`.
 
 :warning: The sub-folder [`core/mem`](https://github.com/stnolting/neorv32/tree/main/rtl/core/mem)
 contains the _platform-agnostic_ VHDL architectures of the processor-internal memories.
 These files can be replaced by platform-specific memory modules.
 
+### [`legacy`](https://github.com/stnolting/neorv32/tree/main/rtl/legacy)
+
+This folder contains RTL modules that were used in older versions of the processor and have
+been deprecated or were never actually used. However, they might still be useful for building
+custom processor setups.
 
 ### [`processor_templates`](https://github.com/stnolting/neorv32/tree/main/rtl/processor_templates)
 
 Contains pre-configured "SoC" templates that instantiate the processor's top entity from `core`.
 These templates can be instantiated directly within a FPGA-specific board wrapper.
 
-
 ### [`system_integration`](https://github.com/stnolting/neorv32/tree/main/rtl/system_integration)
 
-Top entities in this folder provide the same peripheral/IO signals and configuration generics as the default
-processor top entity from `core`, but feature a different interface type.
-For example: an **AXI4-Lite**-compatible bus interface instead of the default Wishbone bus interface
-or a top entity with _resolved_ port signal types.
-
+Top entities in this folder provide the same peripheral/IO signals and configuration generics as
+the default processor top entity from `core`, but featuring a different interface.
 
 ### [`test_setups`](https://github.com/stnolting/neorv32/tree/main/rtl/test_setups)
 
-Minimal test setups (FPGA- and board-independent) for the processor. See the
+Minimal processor test setups (FPGA- and board-independent. See the
 [README](https://github.com/stnolting/neorv32/tree/main/rtl/test_setups)
 in that folder for more information. Note that these test setups are used in the
 [NEORV32 User Guide](https://stnolting.github.io/neorv32/ug).