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[sw\example\cpu_test] clean-up; added HPM tests
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stnolting
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1 changed files with 62 additions and 130 deletions
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@ -3,7 +3,7 @@
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// # ********************************************************************************************* #
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// # BSD 3-Clause License #
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// # #
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// # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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// # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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// # #
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// # Redistribution and use in source and binary forms, with or without modification, are #
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// # permitted provided that the following conditions are met: #
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@ -74,6 +74,8 @@ int cnt_ok = 0;
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int cnt_test = 0;
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/// Global timestamp for traps (stores mcycle.low on trap enter)
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uint32_t trap_timestamp32 = 0;
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/// Global numbe rof available HPMs
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uint32_t num_hpm_cnts_global = 0;
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/**********************************************************************//**
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@ -122,14 +124,8 @@ void sim_trigger_mei(void) {
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int main() {
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register uint32_t tmp_a, tmp_b;
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int i;
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volatile uint32_t dummy_dst __attribute__((unused));
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union {
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uint64_t uint64;
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uint32_t uint32[sizeof(uint64_t)/2];
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} cpu_systime;
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// init UART at default baud rate, no parity bits, no rx interrupt, no tx interrupt
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neorv32_uart_setup(BAUD_RATE, 0b00, 0, 0);
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@ -181,9 +177,6 @@ int main() {
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// show project credits
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neorv32_rte_print_credits();
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// show project license
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neorv32_rte_print_license();
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// show full HW config report
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neorv32_rte_print_hw_config();
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@ -240,63 +233,6 @@ int main() {
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neorv32_cpu_eint();
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// ----------------------------------------------------------
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// List all accessible CSRs
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// ----------------------------------------------------------
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neorv32_cpu_csr_write(CSR_MCAUSE, 0);
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neorv32_uart_printf("[%i] List all accessible CSRs: ", cnt_test);
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if ((UART_CT & (1 << UART_CT_SIM_MODE)) == 0) { // check if this is a simulation
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cnt_test++;
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i = 0;
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neorv32_uart_printf("\n");
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uint32_t csr_addr_cnt = 0;
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// create test program in RAM
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static const uint32_t csr_access_test_program[2] __attribute__((aligned(8))) = {
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0x00006073, // csrrsi, 0x000, 0
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0x00008067 // ret (32-bit)
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};
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// base address of program
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tmp_a = (uint32_t)&csr_access_test_program;
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uint32_t *csr_pnt = (uint32_t*)tmp_a;
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// iterate through full 12-bit CSR address space
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for (csr_addr_cnt=0x000; csr_addr_cnt<=0xfff; csr_addr_cnt++) {
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neorv32_cpu_csr_write(CSR_MCAUSE, 0);
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// construct and store new CSR access instruction
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// 0x00006073 = csrrsi, 0x000, 0
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*csr_pnt = 0x00006073 | (csr_addr_cnt << 20); // insert current CSR address into most significant 12 bits
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// sync instruction stream
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asm volatile("fence.i");
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// execute test program
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asm volatile ("jalr ra, %[input_i]" : : [input_i] "r" (tmp_a));
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// check for access exception
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if (neorv32_cpu_csr_read(CSR_MCAUSE) == 0) { // no exception -> access ok -> CSR exists
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neorv32_uart_printf(" + 0x%x\n", csr_addr_cnt);
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i++;
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}
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}
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if (i != 0) { // at least one CSR was accessible
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test_ok();
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}
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else {
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test_fail();
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}
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}
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else {
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neorv32_uart_printf("skipped (disabled for simulation)\n");
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}
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// ----------------------------------------------------------
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// Test standard RISC-V performance counter [m]cycle[h]
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// ----------------------------------------------------------
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@ -424,6 +360,43 @@ int main() {
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neorv32_cpu_csr_write(CSR_MCOUNTEREN, tmp_a);
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// ----------------------------------------------------------
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// Test performance counter: setup as many events and counter as feasible
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// ----------------------------------------------------------
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neorv32_cpu_csr_write(CSR_MCAUSE, 0);
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neorv32_uart_printf("[%i] Initializing HPMs: ", cnt_test);
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num_hpm_cnts_global = neorv32_cpu_hpm_get_counters();
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if (num_hpm_cnts_global != 0) {
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cnt_test++;
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neorv32_cpu_csr_write(CSR_MHPMCOUNTER3, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT3, 1 << HPMCNT_EVENT_CIR);
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neorv32_cpu_csr_write(CSR_MHPMCOUNTER4, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT4, 1 << HPMCNT_EVENT_WAIT_IF);
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neorv32_cpu_csr_write(CSR_MHPMCOUNTER5, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT5, 1 << HPMCNT_EVENT_LOAD);
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neorv32_cpu_csr_write(CSR_MHPMCOUNTER6, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT6, 1 << HPMCNT_EVENT_STORE);
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neorv32_cpu_csr_write(CSR_MHPMCOUNTER7, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT7, 1 << HPMCNT_EVENT_WAIT_LS);
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neorv32_cpu_csr_write(CSR_MHPMCOUNTER8, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT8, 1 << HPMCNT_EVENT_JUMP);
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neorv32_cpu_csr_write(CSR_MHPMCOUNTER9, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT9, 1 << HPMCNT_EVENT_BRANCH);
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neorv32_cpu_csr_write(CSR_MHPMCOUNTER10, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT10, 1 << HPMCNT_EVENT_TBRANCH);
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neorv32_cpu_csr_write(CSR_MHPMCOUNTER11, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT11, 1 << HPMCNT_EVENT_TRAP);
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neorv32_cpu_csr_write(CSR_MHPMCOUNTER12, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT12, 1 << HPMCNT_EVENT_ILLEGAL);
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neorv32_cpu_csr_write(CSR_MCOUNTINHIBIT, 0); // enable all counters
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// make sure there was no exception
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if (neorv32_cpu_csr_read(CSR_MCAUSE) == 0) {
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test_ok();
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}
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else {
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test_fail();
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}
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}
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else {
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neorv32_uart_printf("skipped (not implemented)\n");
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}
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// ----------------------------------------------------------
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// Bus timeout latency estimation
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// ----------------------------------------------------------
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@ -435,9 +408,9 @@ int main() {
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neorv32_cpu_csr_write(CSR_MCYCLE, 0);
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// this store access will timeout
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MMR_UNREACHABLE = 0; // trap handler will stor mcycle.low to "trap_timestamp32"
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MMR_UNREACHABLE = 0; // trap handler will store mcycle.low to "trap_timestamp32"
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// make sure there was a time-out
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// make sure there was a timeout
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if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_S_ACCESS) {
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neorv32_uart_printf("~%u cycles ", trap_timestamp32-178); // remove trap handler overhead - empiric value ;)
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test_ok();
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@ -495,66 +468,6 @@ int main() {
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}
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// ----------------------------------------------------------
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// Test time (must be == MTIME.TIME)
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// ----------------------------------------------------------
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neorv32_uart_printf("[%i] Time (MTIME.time vs CSR.time) sync: ", cnt_test);
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cnt_test++;
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cpu_systime.uint64 = neorv32_cpu_get_systime();
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uint64_t mtime_systime = neorv32_mtime_get_time();
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// compute difference
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mtime_systime = mtime_systime - cpu_systime.uint64;
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if (mtime_systime < 4096) { // diff should be pretty small depending on bus latency
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test_ok();
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}
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else {
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test_fail();
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}
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// ----------------------------------------------------------
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// Test fence instructions - make sure CPU does not crash here and throws no exception
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// ----------------------------------------------------------
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neorv32_cpu_csr_write(CSR_MCAUSE, 0);
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neorv32_uart_printf("[%i] FENCE instruction test: ", cnt_test);
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cnt_test++;
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asm volatile ("fence");
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if (neorv32_cpu_csr_read(CSR_MCAUSE) != 0) {
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test_fail();
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}
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else {
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test_ok();
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}
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// ----------------------------------------------------------
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// Test fencei instructions - make sure CPU does not crash here and throws no exception
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// a more complex test is provided by the RISC-V compliance test
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// ----------------------------------------------------------
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neorv32_cpu_csr_write(CSR_MCAUSE, 0);
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neorv32_uart_printf("[%i] FENCE.I instruction test: ", cnt_test);
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asm volatile ("fence.i");
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if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_I_ILLEGAL) {
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neorv32_uart_printf("skipped (not implemented)\n");
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}
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else {
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cnt_test++;
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neorv32_cpu_csr_write(CSR_MCAUSE, 0);
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asm volatile ("fence.i");
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if (neorv32_cpu_csr_read(CSR_MCAUSE) == 0) {
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test_ok();
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}
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else {
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test_fail();
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}
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}
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// ----------------------------------------------------------
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// Illegal CSR access (CSR not implemented)
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// ----------------------------------------------------------
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@ -1324,7 +1237,7 @@ int main() {
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neorv32_uart_printf("[%i] Physical memory protection (PMP): ", cnt_test);
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// check if PMP is implemented
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if (neorv32_cpu_csr_read(CSR_MZEXT) & (1<<CSR_MZEXT_PMP)) {
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if (neorv32_cpu_pmp_get_num_regions() != 0) {
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// Test access to protected region
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// ---------------------------------------------
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@ -1571,6 +1484,25 @@ int main() {
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#endif
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// ----------------------------------------------------------
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// HPM reports
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// ----------------------------------------------------------
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neorv32_cpu_csr_write(CSR_MCOUNTINHIBIT, -1); // stop all counters
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neorv32_uart_printf("\n\nHPM results:\n");
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if (num_hpm_cnts_global == 0) {neorv32_uart_printf("no HPMs available\n"); }
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if (num_hpm_cnts_global > 0) {neorv32_uart_printf("# Retired compr. instructions: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER3)); }
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if (num_hpm_cnts_global > 1) {neorv32_uart_printf("# I-fetch wait cycles: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER4)); }
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if (num_hpm_cnts_global > 2) {neorv32_uart_printf("# Load operations: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER5)); }
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if (num_hpm_cnts_global > 3) {neorv32_uart_printf("# Store operations: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER6)); }
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if (num_hpm_cnts_global > 4) {neorv32_uart_printf("# Load/store wait cycles: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER7)); }
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if (num_hpm_cnts_global > 5) {neorv32_uart_printf("# Unconditional jumps: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER8)); }
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if (num_hpm_cnts_global > 6) {neorv32_uart_printf("# Conditional branches (all): %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER9)); }
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if (num_hpm_cnts_global > 7) {neorv32_uart_printf("# Conditional branches (taken): %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER10)); }
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if (num_hpm_cnts_global > 8) {neorv32_uart_printf("# Entered traps: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER11)); }
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if (num_hpm_cnts_global > 9) {neorv32_uart_printf("# Illegal operations: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER12)); }
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neorv32_uart_printf("\n");
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// ----------------------------------------------------------
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// Final test reports
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// ----------------------------------------------------------
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