[docs] remove IRQ ACK/clear via mip

mip CSR is read-only; all interrupts (including FIRQs) are cleared by source-specific mechanism (e.g. writing to a specific memory-mapped register)

docs/datasheet/soc.adoc

@@ -398,6 +398,11 @@ module-internal reset of the remaining logic.
 
 The NEORV32 Processor provides several interrupt request signals (IRQs) for custom platform use.
 
+.Trigger Type
+[IMPORTANT]
+All interrupt request lines are **level-triggered and high-active**. Once set, the signal should remain high until
+the interrupt request is explicitly acknowledged (e.g. writing to a memory-mapped register).
+
 
 :sectnums:
 ==== RISC-V Standard Interrupts
@@ -416,12 +421,6 @@ specifications. However, bare-metal system can also repurpose these interrupts.
 | `mext_irq_i`  | Machine external interrupt (`MEI`). This interrupt is used for any processor-external interrupt source (like a platform interrupt controller).
 |=======================
 
-.Trigger Type
-[IMPORTANT]
-The RISC-V standard interrupts are **level-triggered and high-active**. Once set, the signal has to remain high until
-the interrupt request is explicitly acknowledged (e.g. writing to a memory-mapped register). The RISC-V standard interrupts
-**CANNOT** be acknowledged/cleared by writing zero to the according <<_mip>> CSR bit.
-
 
 :sectnums:
 ==== NEORV32-Specific Fast Interrupt Requests
@@ -457,11 +456,6 @@ table (the channel number also corresponds to the according FIRQ priority: 0 = h
 | 15      | - | _reserved_
 |=======================
 
-.Trigger Type
-[IMPORTANT]
-The fast interrupt request channels become pending after being triggering by one-cycle-high signal.
-A pending FIRQ has to be explicitly cleared by writing zero to the according <<_mip>> CSR bit.
-
 
 <<<
 // ####################################################################################################################

docs/datasheet/soc_cfs.adoc

@@ -61,8 +61,6 @@ int temp = (int)NEORV32_CFS->REG[20]; // read from CFS register 20
 **CFS Interrupt**
 
 The CFS provides a single high-level-triggered interrupt request signal mapped to the CPU's fast interrupt channel 1.
-Once triggered, the interrupt becomes pending (if enabled in the <<_mie>> CSR) and has to be explicitly cleared again by
-writing zero to the according <<_mip>> CSR bit. See section <<_processor_interrupts>> for more information.
 
 
 **CFS Configuration Generic**

docs/datasheet/soc_dma.adoc

@@ -123,8 +123,7 @@ This automatic fencing is enabled by the setting the control register's `DMA_CTR
 **DMA Interrupt**
 
 The DMA features a single CPU interrupt that is triggered when the programmed transfer has completed. This
-interrupt is also triggered if the DMA encounters a bus error during operation. An active DMA interrupt has to be
-explicitly cleared again by clearing `DMA_CTRL_DONE` and also by writing zero to the according <<_mip>> CSR bit.
+interrupt is also triggered if the DMA encounters a bus error during operation.
 
 
 **Register Map**

docs/datasheet/soc_gptmr.adoc

@@ -68,8 +68,7 @@ This stabilized signal is then fed to the edge detection logic.
 
 The GPTRM provides a single interrupt line that can be trigger by a timer-match event and/or by a timer-compare
 event. Once triggered, the interrupt will stay active until explicitly cleared by writing zero to the according
-interrupt flag (`GPTMR_CTRL_TRIGM` or `GPTMR_CTRL_TRIGC`), Additionally, the interrupt has to be also cleared
-again by writing zero to the according <<_mip>> CSR bit(s).
+interrupt flag (`GPTMR_CTRL_TRIGM` or `GPTMR_CTRL_TRIGC`).
 
 
 **Register Map**

docs/datasheet/soc_neoled.adoc

@@ -176,9 +176,6 @@ In this case software can write up to `IO_NEOLED_TX_FIFO`/2 new data words to `D
 status flags. If `NEOLED_CTRL_IRQ_CONF` is cleared, an interrupt is generated when the TX FIFO is empty.
 
 Once the NEOLED interrupt has fired it remains pending until the actual cause of the interrupt is resolved.
-Furthermore, an active NEOLED interrupt has to be explicitly cleared again by writing zero to the according
-<<_mip>> CSR bit.
-
 
 
 **Register Map**

docs/datasheet/soc_onewire.adoc

@@ -5,7 +5,7 @@
 [cols="<3,<3,<4"]
 [frame="topbot",grid="none"]
 |=======================
-| Hardware source file(s): | neorv32_onewire.vhd | 
+| Hardware source file(s): | neorv32_onewire.vhd |
 | Software driver file(s): | neorv32_onewire.c |
 |                          | neorv32_onewire.h |
 | Top entity port:         | `onewire_i` | 1-bit 1-wire bus sense input
@@ -76,7 +76,7 @@ operation to allow the accessed device to pull-down the bus. Accordingly, `DATA`
 triggering the byte transmission operation when the controller shall read a byte from the bus.
 
 The `ONEWIRE_CTRL_PRESENCE` bit gets set if at least one device has send a "presence" signal right after the
-reset pulse. 
+reset pulse.
 
 
 **Bus Timing**
@@ -164,8 +164,7 @@ time **T~base~** (and by eventually changing the hardwired timing configuration
 **Interrupt**
 
 A single interrupt is provided by the ONEWIRE module to signal "idle" condition to the CPU. Whenever the
-controller is idle (again) the interrupt becomes active. Once triggered, the interrupt has to be _explicitly_
-cleared again by writing zero to the according <<_mip>> CSR FIRQ bit.
+controller is idle (again) the interrupt becomes active.
 
 
 **Register Map**

docs/datasheet/soc_sdi.adoc

@@ -5,7 +5,7 @@
 [cols="<3,<3,<4"]
 [frame="topbot",grid="none"]
 |=======================
-| Hardware source file(s): | neorv32_sdi.vhd | 
+| Hardware source file(s): | neorv32_sdi.vhd |
 | Software driver file(s): | neorv32_sdi.c |
 |                          | neorv32_sdi.h |
 | Top entity port:         | `sdi_clk_i` | 1-bit serial clock input
@@ -71,8 +71,6 @@ conditions are logically OR-ed so any enabled interrupt source will trigger the
 
 Once the SDI interrupt has fired it will remain active until the actual cause of the interrupt is resolved; for
 example if just the `SDI_CTRL_IRQ_RX_AVAIL` bit is set, the interrupt will keep firing until the RX FIFO is empty again.
-Furthermore, an active SDI interrupt has to be explicitly cleared again by writing zero to the according
-<<_mip>> CSR bit.
 
 
 **Register Map**

docs/datasheet/soc_slink.adoc

@@ -83,8 +83,6 @@ The current status of the RX and TX FIFOs can be determined via the `SLINK_CTRL_
 A single global interrupt can be programmed based on these FIFO status flags via the control register's `SLINK_CTRL_IRQ_*`
 bits. Note that all enabled interrupt conditions are logically OR-ed. If any enable interrupt conditions becomes true the
 interrupt will become pending until the interrupt-causing condition is resolved (e.g. by reading from the RX FIFO).
-Once the SLINK's interrupt has become pending, it has to be also explicitly cleared again by writing zero to the according
-<<_mip>> CSR bit(s).
 
 
 **Register Map**

docs/datasheet/soc_spi.adoc

@@ -105,8 +105,6 @@ conditions are logically OR-ed so any enabled interrupt source will trigger the
 
 Once the SPI interrupt has fired it remains pending until the actual cause of the interrupt is resolved; for
 example if just the `SPI_CTRL_IRQ_RX_AVAIL` bit is set, the interrupt will keep firing until the RX FIFO is empty again.
-Furthermore, an active SPI interrupt has to be explicitly cleared again by writing zero to the according
-<<_mip>> CSR bit.
 
 
 **Register Map**

docs/datasheet/soc_uart.adoc

@@ -75,7 +75,6 @@ half full. Note that all these programmable conditions are logically OR-ed (inte
 
 Once an UART interrupt has fired it remains pending until the actual cause of the interrupt is resolved; for
 example if just the `UART_CTRL_IRQ_RX_NEMPTY` bit is set, the RX interrupt will keep firing until the RX FIFO is empty again.
-Furthermore, a pending UART interrupt has to be explicitly cleared again by writing zero to the according <<_mip>> CSR bit.
 
 .RX/TX FIFO Size
 [TIP]

docs/datasheet/soc_xirq.adoc

@@ -61,7 +61,6 @@ Writing _any_ value to this register will acknowledge the _current_ XIRQ interru
 In order to acknowledge an XIRQ interrupt, the interrupt handler has to...
 * clear the pending XIRQ channel by clearing the according `EIP` bit
 * writing _any_ value to `ESC` to acknowledge the XIRQ interrupt
-* clear the pending CPU FIRQ by clearing the according <<_mip>> CSR bit
 
 
 **Register Map**