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SPI: Change "variable style" by "pointer style"

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emb4fun 2023-02-27 13:18:02 +01:00
parent d9d141359b
commit 32d1799318
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4 changed files with 25 additions and 25 deletions
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2
sw/example/demo_spi/main.c
View file

@ -104,7 +104,7 @@ int main() {
"Type 'help' to see the help menu.\n\n");
// disable and reset SPI module
NEORV32_SPI.CTRL = 0;
NEORV32_SPI->CTRL = 0;
spi_configured = 0; // SPI not configured yet
spi_size = 0;

14
sw/example/demo_spi_irq/drv/neorv32_spi_irq.c
View file

@ -82,7 +82,7 @@ void neorv32_spi_isr(t_neorv32_spi *self) {
case 1: // uint8_t
// read data from SPI from last transfer
for ( ; self->uint32Read<self->uint32Write; (self->uint32Read)++ ) {
((uint8_t *) self->ptrSpiBuf)[self->uint32Read] = (uint8_t) (NEORV32_SPI.DATA & 0xff); // capture from last transfer
((uint8_t *) self->ptrSpiBuf)[self->uint32Read] = (uint8_t) (NEORV32_SPI->DATA & 0xff); // capture from last transfer
}
if ( self->uint32Read == self->uint32Total ) { // transfer done, no new data
neorv32_spi_cs_dis(); // deselect slave
@ -95,13 +95,13 @@ void neorv32_spi_isr(t_neorv32_spi *self) {
for ( ; self->uint32Write<uint32Lim; (self->uint32Write)++ ) {
uint32Buf = 0;
uint32Buf |= ((uint8_t *) self->ptrSpiBuf)[self->uint32Write];
NEORV32_SPI.DATA = uint32Buf; // next transfer
NEORV32_SPI->DATA = uint32Buf; // next transfer
}
break;
case 2: // uint16_t
// read data from SPI from last transfer
for ( ; self->uint32Read<self->uint32Write; (self->uint32Read)++ ) {
((uint16_t *) self->ptrSpiBuf)[self->uint32Read] = (uint16_t) (NEORV32_SPI.DATA & 0xffff); // capture from last transfer
((uint16_t *) self->ptrSpiBuf)[self->uint32Read] = (uint16_t) (NEORV32_SPI->DATA & 0xffff); // capture from last transfer
}
if ( self->uint32Read == self->uint32Total ) { // transfer done, no new data
neorv32_spi_cs_dis(); // deselect slave
@ -114,13 +114,13 @@ void neorv32_spi_isr(t_neorv32_spi *self) {
for ( ; self->uint32Write<uint32Lim; (self->uint32Write)++ ) {
uint32Buf = 0;
uint32Buf |= ((uint16_t *) self->ptrSpiBuf)[self->uint32Write];
NEORV32_SPI.DATA = uint32Buf; // next transfer
NEORV32_SPI->DATA = uint32Buf; // next transfer
}
break;
case 4: // uint32_t
// read data from SPI from last transfer
for ( ; self->uint32Read<self->uint32Write; (self->uint32Read)++ ) {
((uint32_t *) self->ptrSpiBuf)[self->uint32Read] = NEORV32_SPI.DATA; // capture from last transfer
((uint32_t *) self->ptrSpiBuf)[self->uint32Read] = NEORV32_SPI->DATA; // capture from last transfer
}
if ( self->uint32Read == self->uint32Total ) { // transfer done, no new data
neorv32_spi_cs_dis(); // deselect slave
@ -133,7 +133,7 @@ void neorv32_spi_isr(t_neorv32_spi *self) {
for ( ; self->uint32Write<uint32Lim; (self->uint32Write)++ ) {
uint32Buf = 0;
uint32Buf |= ((uint32_t *) self->ptrSpiBuf)[self->uint32Write];
NEORV32_SPI.DATA = uint32Buf; // next transfer
NEORV32_SPI->DATA = uint32Buf; // next transfer
}
break;
default: // unknown
@ -189,7 +189,7 @@ int neorv32_spi_rw(t_neorv32_spi *self, void *spi, uint8_t csn, uint32_t num_ele
return 2; // unsupported byte size
}
(self->uint32Write)++;
NEORV32_SPI.DATA = uint32Buf; // next transfer
NEORV32_SPI->DATA = uint32Buf; // next transfer
return 0; // successful end
}

4
sw/lib/include/neorv32.h
View file

@ -1077,7 +1077,7 @@ enum NEORV32_UART_DATA_enum {
**************************************************************************/
/**@{*/
/** SPI module prototype */
typedef struct __attribute__((packed,aligned(4))) {
typedef volatile struct __attribute__((packed,aligned(4))) {
uint32_t CTRL; /**< offset 0: control register (#NEORV32_SPI_CTRL_enum) */
uint32_t DATA; /**< offset 4: data register */
} neorv32_spi_t;
@ -1086,7 +1086,7 @@ typedef struct __attribute__((packed,aligned(4))) {
#define NEORV32_SPI_BASE (0xFFFFFFA8U)
/** SPI module hardware access (#neorv32_spi_t) */
#define NEORV32_SPI (*((volatile neorv32_spi_t*) (NEORV32_SPI_BASE)))
#define NEORV32_SPI ((neorv32_spi_t*) (NEORV32_SPI_BASE))
/** SPI control register bits */
enum NEORV32_SPI_CTRL_enum {

30
sw/lib/source/neorv32_spi.c
View file

@ -72,7 +72,7 @@ int neorv32_spi_available(void) {
**************************************************************************/
void neorv32_spi_setup(int prsc, int cdiv, int clk_phase, int clk_polarity, int data_size, int irq_config) {
NEORV32_SPI.CTRL = 0; // reset
NEORV32_SPI->CTRL = 0; // reset
uint32_t tmp = 0;
tmp |= (uint32_t)(1 & 0x01) << SPI_CTRL_EN;
@ -83,7 +83,7 @@ void neorv32_spi_setup(int prsc, int cdiv, int clk_phase, int clk_polarity, int
tmp |= (uint32_t)(cdiv & 0x0f) << SPI_CTRL_CDIV0;
tmp |= (uint32_t)(irq_config & 0x03) << SPI_CTRL_IRQ0;
NEORV32_SPI.CTRL = tmp;
NEORV32_SPI->CTRL = tmp;
}
@ -96,7 +96,7 @@ uint32_t neorv32_spi_get_clock_speed(void) {
const uint32_t PRSC_LUT[8] = {2, 4, 8, 64, 128, 1024, 2048, 4096};
uint32_t ctrl = NEORV32_SPI.CTRL;
uint32_t ctrl = NEORV32_SPI->CTRL;
uint32_t prsc_sel = (ctrl >> SPI_CTRL_PRSC0) & 0x7;
uint32_t clock_div = (ctrl >> SPI_CTRL_CDIV0) & 0xf;
@ -110,7 +110,7 @@ uint32_t neorv32_spi_get_clock_speed(void) {
**************************************************************************/
void neorv32_spi_disable(void) {
NEORV32_SPI.CTRL &= ~((uint32_t)(1 << SPI_CTRL_EN));
NEORV32_SPI->CTRL &= ~((uint32_t)(1 << SPI_CTRL_EN));
}
@ -119,7 +119,7 @@ void neorv32_spi_disable(void) {
**************************************************************************/
void neorv32_spi_enable(void) {
NEORV32_SPI.CTRL |= ((uint32_t)(1 << SPI_CTRL_EN));
NEORV32_SPI->CTRL |= ((uint32_t)(1 << SPI_CTRL_EN));
}
@ -130,7 +130,7 @@ void neorv32_spi_enable(void) {
**************************************************************************/
int neorv32_spi_get_fifo_depth(void) {
uint32_t tmp = (NEORV32_SPI.CTRL >> SPI_CTRL_FIFO_LSB) & 0x0f;
uint32_t tmp = (NEORV32_SPI->CTRL >> SPI_CTRL_FIFO_LSB) & 0x0f;
return (int)(1 << tmp);
}
@ -144,10 +144,10 @@ int neorv32_spi_get_fifo_depth(void) {
**************************************************************************/
void neorv32_spi_cs_en(int cs) {
uint32_t tmp = NEORV32_SPI.CTRL;
uint32_t tmp = NEORV32_SPI->CTRL;
tmp &= ~(0xf << SPI_CTRL_CS_SEL0); // clear old configuration
tmp |= (1 << SPI_CTRL_CS_EN) | ((cs & 7) << SPI_CTRL_CS_SEL0); // set new configuration
NEORV32_SPI.CTRL = tmp;
NEORV32_SPI->CTRL = tmp;
}
@ -157,7 +157,7 @@ void neorv32_spi_cs_en(int cs) {
* @note The SPI chip select output lines are HIGH when deactivated.
**************************************************************************/
void neorv32_spi_cs_dis(void) {
NEORV32_SPI.CTRL &= ~(1 << SPI_CTRL_CS_EN);
NEORV32_SPI->CTRL &= ~(1 << SPI_CTRL_CS_EN);
}
@ -171,10 +171,10 @@ void neorv32_spi_cs_dis(void) {
**************************************************************************/
uint32_t neorv32_spi_trans(uint32_t tx_data) {
NEORV32_SPI.DATA = tx_data; // trigger transfer
while((NEORV32_SPI.CTRL & (1<<SPI_CTRL_BUSY)) != 0); // wait for current transfer to finish
NEORV32_SPI->DATA = tx_data; // trigger transfer
while((NEORV32_SPI->CTRL & (1<<SPI_CTRL_BUSY)) != 0); // wait for current transfer to finish
return NEORV32_SPI.DATA;
return NEORV32_SPI->DATA;
}
@ -185,7 +185,7 @@ uint32_t neorv32_spi_trans(uint32_t tx_data) {
**************************************************************************/
void neorv32_spi_put_nonblocking(uint32_t tx_data) {
NEORV32_SPI.DATA = tx_data; // trigger transfer
NEORV32_SPI->DATA = tx_data; // trigger transfer
}
@ -196,7 +196,7 @@ void neorv32_spi_put_nonblocking(uint32_t tx_data) {
**************************************************************************/
uint32_t neorv32_spi_get_nonblocking(void) {
return NEORV32_SPI.DATA;
return NEORV32_SPI->DATA;
}
@ -207,7 +207,7 @@ uint32_t neorv32_spi_get_nonblocking(void) {
**************************************************************************/
int neorv32_spi_busy(void) {
if ((NEORV32_SPI.CTRL & (1<<SPI_CTRL_BUSY)) != 0) {
if ((NEORV32_SPI->CTRL & (1<<SPI_CTRL_BUSY)) != 0) {
return 1;
}
else {