github-mirrors/neorv32
1
0
Fork 0
mirror of https://github.com/stnolting/neorv32.git synced 2025-04-24 06:07:52 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

minor edits and clean-.ups

Browse source
This commit is contained in:
stnolting 2021-06-27 14:54:06 +02:00
parent a7f3c8d35c
commit 3541407c3e
5 changed files with 46 additions and 72 deletions
Download patch file Download diff file Expand all files Collapse all files

2
docs/datasheet/soc_gpio.adoc
View file

@ -11,7 +11,7 @@
| Top entity port: | `gpio_o` | 32-bit parallel output port
| | `gpio_i` | 32-bit parallel input port
| Configuration generics: | _IO_GPIO_EN_ | implement GPIO port when _true_
| CPU interrupts: | FIRQ channel 8 | pin-change interrupt (see <<_processor_interrupts>>)
| CPU interrupts: | fast IRQ channel 8 | pin-change interrupt (see <<_processor_interrupts>>)
|=======================
**Theory of Operation**

5
docs/legal.adoc
View file

@ -98,6 +98,11 @@ If you are using the NEORV32 or parts of the project in some kind of publication
}
----
[TIP]
Each official release of the project (see https://github.com/stnolting/neorv32/releases[releases page]) provides
a _digital object identifiere_ (**DOI**) provided by https://zenodo.org/.
:sectnums!:
=== Acknowledgments

4
rtl/core/neorv32_cpu_control.vhd
View file

@ -461,8 +461,8 @@ begin
generic map (
FIFO_DEPTH => ipb_entries_c, -- number of fifo entries; has to be a power of two; min 1
FIFO_WIDTH => ipb.wdata'length, -- size of data elements in fifo
FIFO_RSYNC => false, -- false = async read; true = sync read
FIFO_SAFE => false -- true = allow read/write only if data available
FIFO_RSYNC => false, -- we NEED to read data asynchronously
FIFO_SAFE => false -- no safe access required (ensured by FIFO-external control)
)
port map (
-- control --

67
rtl/core/neorv32_neoled.vhd
View file

@ -144,22 +144,20 @@ architecture neorv32_neoled_rtl of neorv32_neoled is
type tx_buffer_t is record
we : std_ulogic; -- write enable
re : std_ulogic; -- read enable
wdata : std_ulogic_vector(31 downto 0); -- write data (excluding excluding)
wdata : std_ulogic_vector(31 downto 0); -- write data (excluding mode)
rdata : std_ulogic_vector(31+1 downto 0); -- read data (including mode)
--
w_pnt : std_ulogic_vector(index_size_f(tx_buffer_entries_c) downto 0); -- write pointer
r_pnt : std_ulogic_vector(index_size_f(tx_buffer_entries_c) downto 0); -- read pointer
match : std_ulogic;
empty : std_ulogic;
empty_ff : std_ulogic;
full : std_ulogic;
avail : std_ulogic; -- data available?
free : std_ulogic; -- free entry available?
free_ff : std_ulogic;
empty : std_ulogic;
empty_ff : std_ulogic;
--
data : tx_fifo_t; -- fifo memory
end record;
signal tx_buffer : tx_buffer_t;
signal fifo_clear : std_ulogic;
signal fifo_wdata : std_ulogic_vector(31+1 downto 0);
-- serial transmission engine --
type serial_state_t is (S_IDLE, S_INIT, S_GETBIT, S_PULSE);
@ -246,37 +244,32 @@ begin
-- TX Buffer (FIFO) -----------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
instr_prefetch_buffer: process(clk_i)
begin
if rising_edge(clk_i) then
-- write port --
if (ctrl.enable = '0') then
tx_buffer.w_pnt <= (others => '0');
elsif (tx_buffer.we = '1') then
tx_buffer.w_pnt <= std_ulogic_vector(unsigned(tx_buffer.w_pnt) + 1);
end if;
if (tx_buffer.we = '1') then -- write data
tx_buffer.data(to_integer(unsigned(tx_buffer.w_pnt(tx_buffer.w_pnt'left-1 downto 0)))) <= ctrl.mode & tx_buffer.wdata;
end if;
-- read port --
if (ctrl.enable = '0') then
tx_buffer.r_pnt <= (others => '0');
elsif (tx_buffer.re = '1') then
tx_buffer.r_pnt <= std_ulogic_vector(unsigned(tx_buffer.r_pnt) + 1);
end if;
tx_buffer.rdata <= tx_buffer.data(to_integer(unsigned(tx_buffer.r_pnt(tx_buffer.r_pnt'left-1 downto 0)))); -- sync read
-- status buffer --
tx_buffer.empty_ff <= tx_buffer.empty;
tx_buffer.free_ff <= tx_buffer.free;
end if;
end process instr_prefetch_buffer;
tx_data_fifo: neorv32_fifo
generic map (
FIFO_DEPTH => tx_buffer_entries_c, -- number of fifo entries; has to be a power of two; min 1
FIFO_WIDTH => 32+1, -- size of data elements in fifo
FIFO_RSYNC => true, -- sync read
FIFO_SAFE => false -- no safe access required (ensured by FIFO-external control)
)
port map (
-- control --
clk_i => clk_i, -- clock, rising edge
rstn_i => '1', -- async reset, low-active
clear_i => fifo_clear, -- sync reset, high-active
-- write port --
wdata_i => fifo_wdata, -- write data
we_i => tx_buffer.we, -- write enable
free_o => tx_buffer.free, -- at least one entry is free when set
-- read port --
re_i => tx_buffer.re, -- read enable
rdata_o => tx_buffer.rdata, -- read data
avail_o => tx_buffer.avail -- data available when set
);
-- status --
tx_buffer.match <= '1' when (tx_buffer.r_pnt(tx_buffer.r_pnt'left-1 downto 0) = tx_buffer.w_pnt(tx_buffer.w_pnt'left-1 downto 0)) else '0';
tx_buffer.full <= '1' when (tx_buffer.r_pnt(tx_buffer.r_pnt'left) /= tx_buffer.w_pnt(tx_buffer.w_pnt'left)) and (tx_buffer.match = '1') else '0';
tx_buffer.empty <= '1' when (tx_buffer.r_pnt(tx_buffer.r_pnt'left) = tx_buffer.w_pnt(tx_buffer.w_pnt'left)) and (tx_buffer.match = '1') else '0';
tx_buffer.free <= not tx_buffer.full;
tx_buffer.avail <= not tx_buffer.empty;
-- helper signals --
fifo_clear <= not ctrl.enable;
fifo_wdata <= ctrl.mode & tx_buffer.wdata;
tx_buffer.empty <= not tx_buffer.avail;
-- Buffer Status Flag and IRQ Generator ---------------------------------------------------

40
rtl/core/neorv32_package.vhd
View file

@ -70,10 +70,14 @@ package neorv32_package is
-- Architecture Constants (do not modify!) ------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant data_width_c : natural := 32; -- native data path width - do not change!
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01050704"; -- no touchy!
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01050705"; -- no touchy!
constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off!
constant rf_r0_is_reg_c : boolean := true; -- x0 is a *physical register* that has to be initialized to zero by the CPU
-- External Interface Types ---------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
type sdata_8x32_t is array (0 to 7) of std_ulogic_vector(31 downto 0);
-- Internal Interface Types ---------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
type pmp_ctrl_if_t is array (0 to 63) of std_ulogic_vector(07 downto 0);
@ -245,13 +249,9 @@ package neorv32_package is
--constant reserved_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffb8"; -- base address
--constant reserved_size_c : natural := 2*4; -- module's address space size in bytes
-- Numerically-Controlled Oscillator (NCO) --
constant nco_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffc0"; -- base address
constant nco_size_c : natural := 4*4; -- module's address space size in bytes
constant nco_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffc0";
constant nco_ch0_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffc4";
constant nco_ch1_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffc8";
constant nco_ch2_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffcc";
-- reserved --
--constant reserved_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffc0"; -- base address
--constant reserved_size_c : natural := 4*4; -- module's address space size in bytes
-- Secondary Universal Asynchronous Receiver/Transmitter (UART1) --
constant uart1_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffd0"; -- base address
@ -927,7 +927,6 @@ package neorv32_package is
IO_CFS_CONFIG : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom CFS configuration generic
IO_CFS_IN_SIZE : positive := 32; -- size of CFS input conduit in bits
IO_CFS_OUT_SIZE : positive := 32; -- size of CFS output conduit in bits
IO_NCO_EN : boolean := true; -- implement numerically-controlled oscillator (NCO)?
IO_NEOLED_EN : boolean := true -- implement NeoPixel-compatible smart LED interface (NEOLED)?
);
port (
@ -981,8 +980,6 @@ package neorv32_package is
-- Custom Functions Subsystem IO --
cfs_in_i : in std_ulogic_vector(IO_CFS_IN_SIZE-1 downto 0); -- custom CFS inputs conduit
cfs_out_o : out std_ulogic_vector(IO_CFS_OUT_SIZE-1 downto 0); -- custom CFS outputs conduit
-- NCO output (available if IO_NCO_EN = true) --
nco_o : out std_ulogic_vector(02 downto 0); -- numerically-controlled oscillator channels
-- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) --
neoled_o : out std_ulogic; -- async serial data line
-- System time --
@ -1751,26 +1748,6 @@ package neorv32_package is
);
end component;
-- Component: Numerically-Controlled Oscillator (NCO) -------------------------------------
-- -------------------------------------------------------------------------------------------
component neorv32_nco
port (
-- host access --
clk_i : in std_ulogic; -- global clock line
addr_i : in std_ulogic_vector(31 downto 0); -- address
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
data_i : in std_ulogic_vector(31 downto 0); -- data in
data_o : out std_ulogic_vector(31 downto 0); -- data out
ack_o : out std_ulogic; -- transfer acknowledge
-- clock generator --
clkgen_en_o : out std_ulogic; -- enable clock generator
clkgen_i : in std_ulogic_vector(07 downto 0);
-- NCO output --
nco_o : out std_ulogic_vector(02 downto 0)
);
end component;
-- Component: Smart LED (WS2811/WS2812) Interface (NEOLED) --------------------------------
-- -------------------------------------------------------------------------------------------
component neorv32_neoled
@ -1827,7 +1804,6 @@ package neorv32_package is
IO_WDT_EN : boolean := true; -- implement watch dog timer (WDT)?
IO_TRNG_EN : boolean := true; -- implement true random number generator (TRNG)?
IO_CFS_EN : boolean := true; -- implement custom functions subsystem (CFS)?
IO_NCO_EN : boolean := true; -- implement numerically-controlled oscillator (NCO)?
IO_NEOLED_EN : boolean := true -- implement NeoPixel-compatible smart LED interface (NEOLED)?
);
port (