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[docs/src_adoc/pwm] updated PWM module

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PWM module now allows to configure up to 60 channels
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stnolting 2021-06-04 21:17:30 +02:00
parent 75b60e0080
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docs/datasheet/soc_pwm.adoc
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@ -8,27 +8,40 @@
| Hardware source file(s): | neorv32_pwm.vhd |
| Software driver file(s): | neorv32_pwm.c |
| | neorv32_pwm.h |
| Top entity port: | `pwm_o` | 4-channel PWM output (1-bit per channel)
| Configuration generics: | _IO_PWM_EN_ | implement PWM controller when _true_
| Top entity port: | `pwm_o` | up to 60 PWM output channels (1-bit per channel)
| Configuration generics: | _IO_PWM_NUM_CH_ | number of PWM channels to implement (0..60)
| CPU interrupts: | none |
|=======================
**Theory of Operation**
The PWM controller implements a pulse-width modulation controller with up to 60 independent channels and 8-
bit resolution per channel. The actual number of implemented channels is defined by the _IO_PWM_NUM_CH_ generic.
Setting this generic to zero will completely remove the PWM controller from the design.
The PWM controller implements a pulse-width modulation controller with four independent channels and 8-
bit resolution per channel. It is based on an 8-bit counter with four programmable threshold comparators that
control the actual duty cycle of each channel. The controller can be used to drive a fancy RGB-LED with 24-
The PWM controller is based on an 8-bit base counter with a programmable threshold comparators for each channel
that defines the actual duty cycle. The controller can be used to drive fancy RGB-LEDs with 24-
bit true color, to dim LCD back-lights or even for "analog" control. An external integrator (RC low-pass filter)
can be used to smooth the generated "analog" signals.
**Theory of Operation**
The PWM controller is activated by setting the _PWM_CT_EN_ bit in the module's control register _PWM_CT_. When this
bit is cleared, the unit is reset and all PWM output channels are set to zero.
The 8-bit duty cycle for each channel, which represents the channel's "intensity", is defined via the according 8-bit_ PWM_DUTY_CHx_ byte in the _PWM_DUTY_ register.
Based on the duty cycle _PWM_DUTY_CHx_ the according intensity of each channel can be computed by the following formula:
The 8-bit duty cycle for each channel, which represents the channel's "intensity", is defined via an 8-bit value. The module
provides up to 15 duty cycle registers _PWM_DUTY0_ to _PWM_DUTY14_ (depending on the number of implemented channels).
Each register contains the duty cycle configuration for 4 consecutive channels. For example, the duty cycle of channel 0
is defined via bits 7:0 in _PWM_DUTY0_. The duty cycle of channel 2 is defined via bits 15:0 in _PWM_DUTY0_.
Channel 4's duty cycle is defined via bits 7:0 in _PWM_DUTY1_ and so on.
[NOTE]
Regardless of the configuration of _IO_PWM_NUM_CH_ all module registers can be accessed without raising an exception.
Software can discover the number of available channels by writing 0xff to all duty cycle configuration bytes and
reading those values back. The duty-cycle of channels that were not implemented always reads as zero.
Based on the configured duty cycle the according intensity of the channel can be computed by the following formula:
_**Intensity~x~**_ = _PWM_DUTY_CHx_ / (2^8^)
The frequency of the generated PWM signals is defined by the PWM operating clock. This clock is derived
The base frequency of the generated PWM signals is defined by the PWM core clock. This clock is derived
from the main processor clock and divided by a prescaler via the 3-bit PWM_CT_PRSCx in the unit's control
register. The following prescalers are available:
@ -40,26 +53,27 @@ register. The following prescalers are available:
| Resulting `clock_prescaler` | 2 | 4 | 8 | 64 | 128 | 1024 | 2048 | 4096
|=======================
The resulting PWM frequency is defined by:
The resulting PWM base frequency is defined by:
_**f~PWM~**_ = _f~main~[Hz]_ / (2^8^ * `clock_prescaler`)
[TIP]
A more sophisticated frequency generation option is provided by by the numerically-controlled oscillator
module (see section <<_numerically_controlled_oscillator_nco>>).
<<<
.PWM register map
[cols="<4,<5,<10,^2,<11"]
[cols="<4,<4,<6,^2,<8"]
[options="header",grid="all"]
|=======================
| Address | Name [C] | Bit(s), Name [C] | R/W | Function
.4+<| `0xffffffb8` .4+<| _PWM_CT_ <|`0` _PWM_CT_EN_ ^| r/w <| TWI enable
.4+<| `0xfffffe80` .4+<| _PWM_CT_ <|`0` _PWM_CT_EN_ ^| r/w | PWM enable
<|`1` _PWM_CT_PRSC0_ ^| r/w .3+<| 3-bit clock prescaler select
<|`2` _PWM_CT_PRSC1_ ^| r/w
<|`2` _PWM_CT_PRSC1_ ^| r/w
<|`3` _PWM_CT_PRSC2_ ^| r/w
.4+<| `0xffffffbc` .4+<| _PWM_DUTY_ <|`7:0` _PWM_DUTY_CH0_MSB_ : _PWM_DUTY_CH0_LSB_ ^| r/w <| 8-bit duty cycle for channel 0
<|`15:8` _PWM_DUTY_CH1_MSB_ : _PWM_DUTY_CH1_LSB_ ^| r/w <| 8-bit duty cycle for channel 1
<|`23:16` _PWM_DUTY_CH2_MSB_ : _PWM_DUTY_CH2_LSB_ ^| r/w <| 8-bit duty cycle for channel 2
<|`31:24` _PWM_DUTY_CH3_MSB_ : _PWM_DUTY_CH3_LSB_ ^| r/w <| 8-bit duty cycle for channel 3
.4+<| `0xfffffe84` .4+<| _PWM_DUTY0_ <|`7:0` ^| r/w <| 8-bit duty cycle for channel 0
<|`15:8` ^| r/w <| 8-bit duty cycle for channel 1
<|`23:16` ^| r/w <| 8-bit duty cycle for channel 2
<|`31:24` ^| r/w <| 8-bit duty cycle for channel 3
| ... | ... | ... | r/w | ...
.4+<| `0xfffffebc` .4+<| _PWM_DUTY15_ <|`7:0` ^| r/w <| 8-bit duty cycle for channel 56
<|`15:8` ^| r/w <| 8-bit duty cycle for channel 57
<|`23:16` ^| r/w <| 8-bit duty cycle for channel 58
<|`31:24` ^| r/w <| 8-bit duty cycle for channel 59
|=======================