minor edits, optimizations and clean-ups

rtl/core/neorv32_cpu_cp_muldiv.vhd

@@ -52,8 +52,8 @@ entity neorv32_cpu_cp_muldiv is
     clk_i   : in  std_ulogic; -- global clock, rising edge
     rstn_i  : in  std_ulogic; -- global reset, low-active, async
     ctrl_i  : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
-    -- data input --
     start_i : in  std_ulogic; -- trigger operation
+    -- data input --
     rs1_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
     rs2_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
     -- result and status --

sw/lib/source/neorv32_uart.c

@@ -71,7 +71,7 @@ int neorv32_uart_available(void) {
 /**********************************************************************//**
  * Enable and configure UART.
  *
- * @warning The 'UART_SIM_MODE' compiler flag will redirect all UART TX data to the simulation output. Use this for simulations only!
+ * @warning The 'UART_SIM_MODE' compiler flag will configure UART for simulation mode: all UART TX data will be redirected to simulation output. Use this for simulations only!
  * @warning To enable simulation mode add <USER_FLAGS+=-DUART_SIM_MODE> when compiling.
  *
  * @param[in] baudrate Targeted BAUD rate (e.g. 9600).
@@ -82,14 +82,21 @@ void neorv32_uart_setup(uint32_t baudrate, uint8_t rx_irq, uint8_t tx_irq) {
 
   UART_CT = 0; // reset
 
-  // raw baud rate prescaler
   uint32_t clock = SYSINFO_CLK;
   uint16_t i = 0; // BAUD rate divisor
-  uint8_t p = 0; // prsc = CLK/2
+  uint8_t p = 0; // initial prsc = CLK/2
+
+  // raw clock prescaler
+#ifdef __riscv_div
+  // use div instructions
+  i = (uint16_t)(clock / (2*baudrate));
+#else
+  // division via repeated subtraction
   while (clock >= 2*baudrate) {
     clock -= 2*baudrate;
     i++;
   }
+#endif
 
   // find clock prsc
   while (i >= 0x0fff) {