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🚀 preparing release v1.10.8
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stnolting 2024-12-26 18:10:36 +01:00
parent 32e206563d
commit 3c8ac9ad00
4 changed files with 4 additions and 3 deletions
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1
CHANGELOG.md
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@ -29,6 +29,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
| Date | Version | Comment | Ticket |
|:----:|:-------:|:--------|:------:|
| 26.12.2024 | [**:rocket:1.10.8**](https://github.com/stnolting/neorv32/releases/tag/v1.10.8) | **New release** | |
| 23.12.2024 | 1.10.7.9 | :warning: rework IO/peripheral address space; :sparkles: increase device size from 256 bytes to 64kB | [#1126](https://github.com/stnolting/neorv32/pull/1126) |
| 22.12.2024 | 1.10.7.8 | :warning: rename CPU tuning options / generics | [#1125](https://github.com/stnolting/neorv32/pull/1125) |
| 22.12.2024 | 1.10.7.7 | :warning: move clock gating switch from processor top to CPU clock; `CLOCK_GATING_EN` is now a CPU tuning option | [#1124](https://github.com/stnolting/neorv32/pull/1124) |

2
docs/attrs.adoc
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@ -2,7 +2,7 @@
:email: stnolting@gmail.com
:keywords: neorv32, risc-v, riscv, rv32, fpga, soft-core, vhdl, microcontroller, cpu, soc, processor, gcc, openocd, gdb, verilog, rtl, asip, asic
:description: A size-optimized, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
:revnumber: v1.10.7
:revnumber: v1.10.8
:icons: font
:imagesdir: ../figures
:toc: macro

2
rtl/core/neorv32_package.vhd
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@ -29,7 +29,7 @@ package neorv32_package is
-- Architecture Constants -----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01100709"; -- hardware version
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01100800"; -- hardware version
constant archid_c : natural := 19; -- official RISC-V architecture ID
constant XLEN : natural := 32; -- native data path width

2
sw/svd/neorv32.svd
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@ -4,7 +4,7 @@
<vendor>stnolting</vendor>
<name>neorv32</name>
<series>RISC-V</series>
<version>1.10.7</version>
<version>1.10.8</version>
<description>The NEORV32 RISC-V Processor</description>
<!-- CPU core -->