github-mirrors/neorv32
1
0
Fork 0
mirror of https://github.com/stnolting/neorv32.git synced 2025-04-24 14:17:51 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

[rtl] minor comment fixes
Some checks are pending
Processor / processor simulation (push) Waiting to run
Details

Browse source
This commit is contained in:
stnolting 2025-03-01 06:45:38 +01:00
parent 00294c6c29
commit 3cd192ecd2
4 changed files with 8 additions and 9 deletions
Download patch file Download diff file Expand all files Collapse all files

4
rtl/core/neorv32_cpu.vhd
View file

@ -224,7 +224,7 @@ begin
);
-- Control Unit (Back-End) ----------------------------------------------------------------
-- Control Unit (Back-End / Instruction Execution) ----------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_cpu_control_inst: entity neorv32.neorv32_cpu_control
generic map (
@ -314,7 +314,7 @@ begin
neorv32_cpu_counters_inst: entity neorv32.neorv32_cpu_counters
generic map (
ZICNTR_EN => RISCV_ISA_Zicntr, -- implement base counters
ZIHPM_EN => RISCV_ISA_Zihpm, -- implement hardware performance monitors
ZIHPM_EN => RISCV_ISA_Zihpm, -- implement hardware performance monitors (HPMs)
HPM_NUM => HPM_NUM_CNTS, -- number of implemented HPM counters (0..13)
HPM_WIDTH => HPM_CNT_WIDTH -- total size of HPM counters (0..64)
)

5
rtl/core/neorv32_cpu_control.vhd
View file

@ -1,10 +1,9 @@
-- ================================================================================ --
-- NEORV32 CPU - Central Control Unit --
-- -------------------------------------------------------------------------------- --
-- + Execute engine: Multi-cycle execution of instruction (pipeline stage 2) --
-- + Execute engine: Multi-cycle execution of instructions ("back-end") --
-- + Trap controller: Handles interrupts and exceptions --
-- + CSR module: Read/write access to control and status registers --
-- + CPU counters: Base and HPM counters --
-- + Debug module: CPU debug mode handling (on-chip debugger) --
-- + Trigger module: Hardware-assisted breakpoints (on-chip debugger) --
-- -------------------------------------------------------------------------------- --
@ -532,7 +531,7 @@ begin
exe_engine_nxt.state <= EX_DISPATCH;
end if;
when EX_BRANCHED => -- delay cycle to wait for reset of pipeline front-end (instruction fetch)
when EX_BRANCHED => -- delay cycle to wait for reset of front-end (instruction fetch)
-- ------------------------------------------------------------
exe_engine_nxt.state <= EX_DISPATCH;

4
rtl/core/neorv32_cpu_counters.vhd
View file

@ -136,8 +136,8 @@ begin
rdata_o => cycle_rd
);
-- [m]time[h] CSR --
time_rd <= (others => '0'); -- not implemented (yet?)
-- time[h] CSR --
time_rd <= (others => '0'); -- not implemented
-- [m]instret[h] CSR --
instret_inst: neorv32_cpu_counters_cnt

4
rtl/core/neorv32_debug_dm.vhd
View file

@ -86,7 +86,7 @@ architecture neorv32_debug_dm_rtl of neorv32_debug_dm is
command : std_ulogic_vector(31 downto 0);
--
halt_req : std_ulogic;
req_res : std_ulogic;
req_res : std_ulogic;
reset_ack : std_ulogic;
hartsel : std_ulogic_vector(1+1 downto 0); -- plus one bit to detect "unavailable hart"
hartsel_dec : std_ulogic_vector(NUM_HARTS-1 downto 0);
@ -481,7 +481,7 @@ begin
end if;
end process dmi_write_access;
-- hat select decoder (one-hot) --
-- hart select decoder (one-hot) --
hartsel_decode:
for i in 0 to NUM_HARTS-1 generate
dm_reg.hartsel_dec(i) <= '1' when (dm_reg.hartsel(2) = '0') and (dm_reg.hartsel(1 downto 0) = std_ulogic_vector(to_unsigned(i, 2))) else '0';