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[rte] check for each PMP mode individually

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stnolting 2024-11-02 21:22:15 +01:00
parent 5b41edd253
commit 3cf72cc61c
1 changed files with 9 additions and 6 deletions
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15
sw/lib/source/neorv32_rte.c
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@ -493,21 +493,24 @@ void neorv32_rte_print_hw_config(void) {
neorv32_uart0_printf("\nPhys. Memory Prot.: ");
uint32_t pmp_num_regions = neorv32_cpu_pmp_get_num_regions();
if (pmp_num_regions != 0) {
neorv32_uart0_printf("%u region(s), %u bytes granularity, modes={OFF", pmp_num_regions, neorv32_cpu_pmp_get_granularity());
neorv32_uart0_printf("%u region(s), %u bytes granularity, modes =", pmp_num_regions, neorv32_cpu_pmp_get_granularity());
// check implemented modes
neorv32_cpu_csr_write(CSR_PMPCFG0, (PMP_OFF << PMPCFG_A_LSB)); // try to set mode "OFF"
if ((neorv32_cpu_csr_read(CSR_PMPCFG0) & 0xff) == (PMP_OFF << PMPCFG_A_LSB)) {
neorv32_uart0_printf(" OFF");
}
neorv32_cpu_csr_write(CSR_PMPCFG0, (PMP_TOR << PMPCFG_A_LSB)); // try to set mode "TOR"
if ((neorv32_cpu_csr_read(CSR_PMPCFG0) & 0xff) == (PMP_TOR << PMPCFG_A_LSB)) {
neorv32_uart0_printf(",TOR");
neorv32_uart0_printf(" TOR");
}
neorv32_cpu_csr_write(CSR_PMPCFG0, (PMP_NA4 << PMPCFG_A_LSB)); // try to set mode "NA4"
if ((neorv32_cpu_csr_read(CSR_PMPCFG0) & 0xff) == (PMP_NA4 << PMPCFG_A_LSB)) {
neorv32_uart0_printf(",NA4");
neorv32_uart0_printf(" NA4");
}
neorv32_cpu_csr_write(CSR_PMPCFG0, (PMP_NAPOT << PMPCFG_A_LSB)); // try to set mode "NAPOT"
if ((neorv32_cpu_csr_read(CSR_PMPCFG0) & 0xff) == (PMP_NAPOT << PMPCFG_A_LSB)) {
neorv32_uart0_printf(",NAPOT");
neorv32_uart0_printf(" NAPOT");
}
neorv32_uart0_putc('}');
neorv32_cpu_csr_write(CSR_PMPCFG0, 0); // disable PMP entry again
}
else {
@ -621,7 +624,7 @@ void neorv32_rte_print_hw_config(void) {
if (tmp & (1 << SYSINFO_SOC_XBUS)) {
neorv32_uart0_printf("Wishbone-b4 ");
if (tmp & (1 << SYSINFO_SOC_XBUS_CACHE)) {
neorv32_uart0_printf("x-cache\n");
neorv32_uart0_printf("xbus-cache\n");
}
else {
neorv32_uart0_printf("\n");