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[sim] xbus_gateway: add port enable generics

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stnolting 2024-12-12 22:39:34 +01:00
parent 64d7699537
commit 3ebe1169b4
1 changed files with 15 additions and 10 deletions
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25
sim/xbus_gateway.vhd
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@ -17,11 +17,11 @@ use neorv32.neorv32_package.all;
entity xbus_gateway is
generic (
-- device address size in bytes and base address --
DEV_0_SIZE : natural := 0; DEV_0_BASE : std_ulogic_vector(31 downto 0) := (others => '0');
DEV_1_SIZE : natural := 0; DEV_1_BASE : std_ulogic_vector(31 downto 0) := (others => '0');
DEV_2_SIZE : natural := 0; DEV_2_BASE : std_ulogic_vector(31 downto 0) := (others => '0');
DEV_3_SIZE : natural := 0; DEV_3_BASE : std_ulogic_vector(31 downto 0) := (others => '0')
-- device enable, address size in bytes and base address (word-aligned) --
DEV_0_EN : boolean := false; DEV_0_SIZE : natural := 0; DEV_0_BASE : std_ulogic_vector(31 downto 0) := (others => '0');
DEV_1_EN : boolean := false; DEV_1_SIZE : natural := 0; DEV_1_BASE : std_ulogic_vector(31 downto 0) := (others => '0');
DEV_2_EN : boolean := false; DEV_2_SIZE : natural := 0; DEV_2_BASE : std_ulogic_vector(31 downto 0) := (others => '0');
DEV_3_EN : boolean := false; DEV_3_SIZE : natural := 0; DEV_3_BASE : std_ulogic_vector(31 downto 0) := (others => '0')
);
port (
-- host port --
@ -41,8 +41,10 @@ architecture xbus_gateway_rtl of xbus_gateway is
constant num_devs_c : natural := 4; -- number of device ports
-- list of device base address and address size --
type dev_en_list_t is array (0 to num_devs_c-1) of boolean;
type dev_base_list_t is array (0 to num_devs_c-1) of std_ulogic_vector(31 downto 0);
type dev_size_list_t is array (0 to num_devs_c-1) of natural;
constant dev_en_list_c : dev_en_list_t := (DEV_0_EN, DEV_1_EN, DEV_2_EN, DEV_3_EN);
constant dev_base_list_c : dev_base_list_t := (DEV_0_BASE, DEV_1_BASE, DEV_2_BASE, DEV_3_BASE);
constant dev_size_list_c : dev_size_list_t := (DEV_0_SIZE, DEV_1_SIZE, DEV_2_SIZE, DEV_3_SIZE);
@ -66,7 +68,7 @@ begin
-- device select --
acc_en_gen:
for i in 0 to num_devs_c-1 generate
acc_en(i) <= '1' when (dev_size_list_c(i) > 0) and
acc_en(i) <= '1' when (dev_size_list_c(i) > 0) and dev_en_list_c(i) and
(unsigned(host_req_i.addr) >= unsigned(dev_base_list_c(i))) and
(unsigned(host_req_i.addr) < (unsigned(dev_base_list_c(i)) + dev_size_list_c(i))) else '0';
end generate;
@ -76,9 +78,12 @@ begin
for i in 0 to num_devs_c-1 generate
bus_request: process(host_req_i, acc_en)
begin
dev_req(i) <= host_req_i;
dev_req(i).cyc <= host_req_i.cyc and acc_en(i);
dev_req(i).stb <= host_req_i.stb and acc_en(i);
dev_req(i) <= xbus_req_terminate_c; -- default: disabled
if dev_en_list_c(i) then
dev_req(i) <= host_req_i;
dev_req(i).cyc <= host_req_i.cyc and acc_en(i);
dev_req(i).stb <= host_req_i.stb and acc_en(i);
end if;
end process bus_request;
end generate;
@ -90,7 +95,7 @@ begin
tmp_v.ack := '0';
tmp_v.err := '0';
for i in 0 to num_devs_c-1 loop -- OR all enabled response buses
if (acc_en(i) = '1') then
if (acc_en(i) = '1') and dev_en_list_c(i) then
tmp_v.data := tmp_v.data or dev_rsp(i).data;
tmp_v.ack := tmp_v.ack or dev_rsp(i).ack;
tmp_v.err := tmp_v.err or dev_rsp(i).err;