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[cpu] add inter-core communication links
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stnolting
parent
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commit
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2 changed files with 96 additions and 36 deletions
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@ -62,25 +62,33 @@ type of all signals is _std_ulogic_ or _std_ulogic_vector_, respectively. The "D
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direction as seen from the CPU.
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.NEORV32 CPU Signal List
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[cols="<3,^3,^1,<5"]
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[cols="^2,^2,^1,<8"]
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[options="header", grid="rows"]
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|=======================
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| Signal | Width/Type | Dir | Description
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4+^| **Global Signals**
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| `clk_i` | 1 | in | Global clock line, all registers triggering on rising edge.
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| `rstn_i` | 1 | in | Global reset, low-active.
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| `clk_i` | 1 | in | Global clock line, all registers triggering on rising edge.
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| `rstn_i` | 1 | in | Global reset, low-active.
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4+^| **Interrupts (<<_traps_exceptions_and_interrupts>>)**
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| `msi_i` | 1 | in | RISC-V machine software interrupt.
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| `mei_i` | 1 | in | RISC-V machine external interrupt.
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| `mti_i` | 1 | in | RISC-V machine timer interrupt.
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| `firq_i` | 16 | in | Custom fast interrupt request signals.
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| `dbi_i` | 1 | in | Request CPU to halt and enter debug mode (RISC-V <<_on_chip_debugger_ocd>>).
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| `msi_i` | 1 | in | RISC-V machine software interrupt.
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| `mei_i` | 1 | in | RISC-V machine external interrupt.
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| `mti_i` | 1 | in | RISC-V machine timer interrupt.
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| `firq_i` | 16 | in | Custom fast interrupt request signals.
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| `dbi_i` | 1 | in | Request CPU to halt and enter debug mode (RISC-V <<_on_chip_debugger_ocd>>).
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4+^| **Instruction <<_bus_interface>>**
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| `ibus_req_o` | `bus_req_t` | out | Instruction fetch bus request.
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| `ibus_rsp_i` | `bus_rsp_t` | in | Instruction fetch bus response.
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| `ibus_req_o` | `bus_req_t` | out | Instruction fetch bus request.
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| `ibus_rsp_i` | `bus_rsp_t` | in | Instruction fetch bus response.
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4+^| **Data <<_bus_interface>>**
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| `dbus_req_o` | `bus_req_t` | out | Data access (load/store) bus request.
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| `dbus_rsp_i` | `bus_rsp_t` | in | Data access (load/store) bus response.
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| `dbus_req_o` | `bus_req_t` | out | Data access (load/store) bus request.
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| `dbus_rsp_i` | `bus_rsp_t` | in | Data access (load/store) bus response.
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4+^| **<<_inter_core_communication_icc>> TX links**
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| `icc_tx_rdy_o` | 2 | out | Data available for cores `0..1`.
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| `icc_tx_ack_i` | 2 | in | Read-enable from cores `0..1`.
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| `icc_tx_dat_o` | 2*32 | out | Data for cores `0..1`.
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4+^| **<<_inter_core_communication_icc>> RX links**
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| `icc_rx_rdy_i` | 2 | in | Data available from cores `0..1`.
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| `icc_rx_ack_o` | 2 | out | Read-enable for cores `0..1`.
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| `icc_rx_dat_i` | 2*32 | in | Data from cores `0..1`.
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|=======================
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.Bus Interface Protocol
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@ -109,8 +117,9 @@ The generic type "suv(x:y)" represents a `std_ulogic_vector(x downto y)`.
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[options="header",grid="rows"]
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|=======================
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| Name | Type | Description
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| `HART_ID` | natural | Value for the <<_mhartid>> CSR.
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| `VENDOR_ID` | suv(31:0) | Value for the <<_mvendorid>> CSR.
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| `HART_ID` | natural | ID of the core (for <<_mhartid>> CSR).
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| `NUM_HARTS` | natural | Total number of cores in the system.
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| `VENDOR_ID` | suv(31:0) | Vendor identification (for <<_mvendorid>> CSR).
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| `BOOT_ADDR` | suv(31:0) | CPU reset address. See section <<_address_space>>.
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| `DEBUG_PARK_ADDR` | suv(31:0) | "Park loop" entry address for the <<_on_chip_debugger_ocd>>, has to be 4-byte aligned.
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| `DEBUG_EXC_ADDR` | suv(31:0) | "Exception" entry address for the <<_on_chip_debugger_ocd>>, has to be 4-byte aligned.
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@ -22,7 +22,8 @@ use neorv32.neorv32_package.all;
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entity neorv32_cpu is
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generic (
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-- General --
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HART_ID : natural; -- hardware thread ID
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HART_ID : natural range 0 to 3; -- hardware thread ID
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NUM_HARTS : natural range 1 to 4; -- total number of harts in the system, has to be a power of 2
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VENDOR_ID : std_ulogic_vector(31 downto 0); -- vendor's JEDEC ID
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BOOT_ADDR : std_ulogic_vector(31 downto 0); -- cpu boot address
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DEBUG_PARK_ADDR : std_ulogic_vector(31 downto 0); -- cpu debug mode parking loop entry address
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@ -69,20 +70,28 @@ entity neorv32_cpu is
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);
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port (
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-- global control --
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clk_i : in std_ulogic; -- switchable global clock, rising edge
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rstn_i : in std_ulogic; -- global reset, low-active, async
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clk_i : in std_ulogic; -- switchable global clock, rising edge
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rstn_i : in std_ulogic; -- global reset, low-active, async
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-- interrupts --
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msi_i : in std_ulogic; -- risc-v machine software interrupt
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mei_i : in std_ulogic; -- risc-v machine external interrupt
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mti_i : in std_ulogic; -- risc-v machine timer interrupt
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firq_i : in std_ulogic_vector(15 downto 0); -- custom fast interrupts
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dbi_i : in std_ulogic; -- risc-v debug halt request interrupt
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msi_i : in std_ulogic; -- risc-v machine software interrupt
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mei_i : in std_ulogic; -- risc-v machine external interrupt
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mti_i : in std_ulogic; -- risc-v machine timer interrupt
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firq_i : in std_ulogic_vector(15 downto 0); -- custom fast interrupts
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dbi_i : in std_ulogic; -- risc-v debug halt request interrupt
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-- instruction bus interface --
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ibus_req_o : out bus_req_t; -- request bus
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ibus_rsp_i : in bus_rsp_t; -- response bus
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ibus_req_o : out bus_req_t; -- request bus
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ibus_rsp_i : in bus_rsp_t; -- response bus
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-- data bus interface --
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dbus_req_o : out bus_req_t; -- request bus
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dbus_rsp_i : in bus_rsp_t -- response bus
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dbus_req_o : out bus_req_t; -- request bus
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dbus_rsp_i : in bus_rsp_t; -- response bus
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-- ICC TX links --
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icc_tx_rdy_o : out std_ulogic_vector(NUM_HARTS-1 downto 0); -- data available
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icc_tx_ack_i : in std_ulogic_vector(NUM_HARTS-1 downto 0); -- read-enable
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icc_tx_dat_o : out std_ulogic_vector((NUM_HARTS*XLEN)-1 downto 0); -- data word
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-- ICC RX links --
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icc_rx_rdy_i : in std_ulogic_vector(NUM_HARTS-1 downto 0); -- data available
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icc_rx_ack_o : out std_ulogic_vector(NUM_HARTS-1 downto 0); -- read-enable
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icc_rx_dat_i : in std_ulogic_vector((NUM_HARTS*XLEN)-1 downto 0) -- data word
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);
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end neorv32_cpu;
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@ -98,12 +107,14 @@ architecture neorv32_cpu_rtl of neorv32_cpu is
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RISCV_ISA_Zksh and RISCV_ISA_Zksed; -- Zks: ShangMi suite
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-- external CSR interface --
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signal xcsr_re : std_ulogic;
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signal xcsr_we : std_ulogic;
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signal xcsr_addr : std_ulogic_vector(11 downto 0);
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signal xcsr_wdata : std_ulogic_vector(XLEN-1 downto 0);
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signal xcsr_rdata_pmp : std_ulogic_vector(XLEN-1 downto 0);
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signal xcsr_rdata_alu : std_ulogic_vector(XLEN-1 downto 0);
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signal xcsr_rdata_res : std_ulogic_vector(XLEN-1 downto 0);
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signal xcsr_rdata_icc : std_ulogic_vector(XLEN-1 downto 0);
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-- local signals --
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signal clk_gated : std_ulogic; -- switchable clock (clock gating)
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@ -128,7 +139,7 @@ architecture neorv32_cpu_rtl of neorv32_cpu is
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begin
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-- Sanity Checks --------------------------------------------------------------------------
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-- Configuration Info and Sanity Checks ---------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- CPU ISA configuration (in alphabetical order - not in canonical order!) --
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assert false report "[NEORV32] CPU ISA: rv32" &
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@ -177,6 +188,10 @@ begin
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-- simulation notifier --
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assert not is_simulation_c report "[NEORV32] Assuming this is a simulation." severity warning;
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-- ID checks --
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assert is_power_of_two_f(NUM_HARTS) report "[NEORV32] NUM_HARTS has to be a power of two." severity error;
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assert (HART_ID < NUM_HARTS) report "[NEORV32] HART_ID out of range." severity error;
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-- Clock Gating ---------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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@ -197,7 +212,7 @@ begin
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end generate;
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-- Control Unit ---------------------------------------------------------------------------
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-- Control Unit (CTRL) --------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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neorv32_cpu_control_inst: entity neorv32.neorv32_cpu_control
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generic map (
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@ -269,7 +284,7 @@ begin
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csr_rdata_o => csr_rdata, -- CSR read data
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-- external CSR interface --
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xcsr_we_o => xcsr_we, -- global write enable
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xcsr_re_o => open, -- global read enable
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xcsr_re_o => xcsr_re, -- global read enable
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xcsr_addr_o => xcsr_addr, -- address
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xcsr_wdata_o => xcsr_wdata, -- write data
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xcsr_rdata_i => xcsr_rdata_res, -- read data
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@ -287,10 +302,10 @@ begin
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irq_machine <= mti_i & mei_i & msi_i;
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-- external CSR read-back --
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xcsr_rdata_res <= xcsr_rdata_pmp or xcsr_rdata_alu;
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xcsr_rdata_res <= xcsr_rdata_alu or xcsr_rdata_pmp or xcsr_rdata_icc;
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-- Register File --------------------------------------------------------------------------
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-- Register File (RF) ---------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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neorv32_cpu_regfile_inst: entity neorv32.neorv32_cpu_regfile
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generic map (
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@ -314,7 +329,7 @@ begin
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rf_wdata <= alu_res or lsu_rdata or csr_rdata or pc_ret;
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-- ALU (Arithmetic/Logic Unit) and ALU Co-Processors --------------------------------------
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-- Arithmetic/Logic Unit (ALU) and ALU Co-Processors --------------------------------------
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-- -------------------------------------------------------------------------------------------
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neorv32_cpu_alu_inst: entity neorv32.neorv32_cpu_alu
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generic map (
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@ -364,7 +379,7 @@ begin
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);
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-- Load/Store Unit ------------------------------------------------------------------------
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-- Load/Store Unit (LSU) ------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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neorv32_cpu_lsu_inst: entity neorv32.neorv32_cpu_lsu
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generic map (
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@ -389,9 +404,9 @@ begin
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);
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-- Physical Memory Protection -------------------------------------------------------------
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-- Physical Memory Protection (PMP) -------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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pmp_inst_true:
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pmp_enabled:
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if RISCV_ISA_Smpmp generate
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neorv32_cpu_pmp_inst: entity neorv32.neorv32_cpu_pmp
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generic map (
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@ -418,11 +433,47 @@ begin
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);
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end generate;
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pmp_inst_false:
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pmp_disabled:
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if not RISCV_ISA_Smpmp generate
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xcsr_rdata_pmp <= (others => '0');
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pmp_fault <= '0';
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end generate;
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-- Inter-Core Communication (ICC) ---------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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icc_enabled:
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if NUM_HARTS > 1 generate
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neorv32_cpu_icc_inst: entity neorv32.neorv32_cpu_icc
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generic map (
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HART_ID => HART_ID, -- ID of this core
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NUM_HARTS => NUM_HARTS -- number of cores, has to be a power of two
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)
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port map (
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-- global control --
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clk_i => clk_i, -- global clock, rising edge
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rstn_i => rstn_i, -- global reset, low-active, async
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-- CSR interface --
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csr_we_i => xcsr_we, -- global write enable
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csr_re_i => xcsr_re, -- global read enable
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csr_addr_i => xcsr_addr, -- address
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csr_wdata_i => xcsr_wdata, -- write data
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csr_rdata_o => xcsr_rdata_icc, -- read data
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-- ICC TX links --
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icc_tx_rdy_o => icc_tx_rdy_o, -- data available
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icc_tx_ack_i => icc_tx_ack_i, -- read-enable
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icc_tx_dat_o => icc_tx_dat_o, -- data word
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-- ICC RX links --
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icc_rx_rdy_i => icc_rx_rdy_i, -- data available
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icc_rx_ack_o => icc_rx_ack_o, -- read-enable
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icc_rx_dat_i => icc_rx_dat_i -- data word
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);
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end generate;
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icc_disabled:
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if NUM_HARTS = 1 generate
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xcsr_rdata_icc <= (others => '0');
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end generate;
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end neorv32_cpu_rtl;
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