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[sw] update SPI HAL
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stnolting
parent
6f7fb6fea5
commit
3ffc84cb76
4 changed files with 96 additions and 90 deletions
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@ -1067,32 +1067,34 @@ typedef volatile struct __attribute__((packed,aligned(4))) {
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/** SPI control register bits */
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enum NEORV32_SPI_CTRL_enum {
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SPI_CTRL_EN = 0, /**< SPI control register(0) (r/w): SPI unit enable */
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SPI_CTRL_CPHA = 1, /**< SPI control register(1) (r/w): Clock phase */
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SPI_CTRL_CPOL = 2, /**< SPI control register(2) (r/w): Clock polarity */
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SPI_CTRL_SIZE0 = 3, /**< SPI control register(3) (r/w): Transfer data size lsb (00: 8-bit, 01: 16-bit, 10: 24-bit, 11: 32-bit) */
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SPI_CTRL_SIZE1 = 4, /**< SPI control register(4) (r/w): Transfer data size msb (00: 8-bit, 01: 16-bit, 10: 24-bit, 11: 32-bit) */
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SPI_CTRL_CS_SEL0 = 5, /**< SPI control register(5) (r/w): Direct chip select bit 1 */
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SPI_CTRL_CS_SEL1 = 6, /**< SPI control register(6) (r/w): Direct chip select bit 2 */
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SPI_CTRL_CS_SEL2 = 7, /**< SPI control register(7) (r/w): Direct chip select bit 2 */
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SPI_CTRL_CS_EN = 8, /**< SPI control register(8) (r/w): Chip select enable (selected CS line output is low when set) */
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SPI_CTRL_PRSC0 = 9, /**< SPI control register(9) (r/w): Clock prescaler select bit 0 */
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SPI_CTRL_PRSC1 = 10, /**< SPI control register(10) (r/w): Clock prescaler select bit 1 */
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SPI_CTRL_PRSC2 = 11, /**< SPI control register(11) (r/w): Clock prescaler select bit 2 */
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SPI_CTRL_CDIV0 = 12, /**< SPI control register(12) (r/w): Clock divider bit 0 */
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SPI_CTRL_CDIV1 = 13, /**< SPI control register(13) (r/w): Clock divider bit 1 */
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SPI_CTRL_CDIV2 = 14, /**< SPI control register(14) (r/w): Clock divider bit 2 */
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SPI_CTRL_CDIV3 = 15, /**< SPI control register(15) (r/w): Clock divider bit 3 */
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SPI_CTRL_IRQ0 = 16, /**< SPI control register(16) (r/w): Interrupt configuration lsb (0-: PHY going idle) */
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SPI_CTRL_IRQ1 = 17, /**< SPI control register(17) (r/w): Interrupt configuration lsb (10: TX fifo less than half full, 11: TX fifo empty) */
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SPI_CTRL_EN = 0, /**< SPI control register(0) (r/w): SPI unit enable */
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SPI_CTRL_CPHA = 1, /**< SPI control register(1) (r/w): Clock phase */
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SPI_CTRL_CPOL = 2, /**< SPI control register(2) (r/w): Clock polarity */
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SPI_CTRL_CS_SEL0 = 3, /**< SPI control register(3) (r/w): Direct chip select bit 1 */
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SPI_CTRL_CS_SEL1 = 4, /**< SPI control register(4) (r/w): Direct chip select bit 2 */
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SPI_CTRL_CS_SEL2 = 5, /**< SPI control register(5) (r/w): Direct chip select bit 2 */
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SPI_CTRL_CS_EN = 6, /**< SPI control register(6) (r/w): Chip select enable (selected CS line output is low when set) */
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SPI_CTRL_PRSC0 = 7, /**< SPI control register(7) (r/w): Clock prescaler select bit 0 */
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SPI_CTRL_PRSC1 = 8, /**< SPI control register(8) (r/w): Clock prescaler select bit 1 */
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SPI_CTRL_PRSC2 = 9, /**< SPI control register(9) (r/w): Clock prescaler select bit 2 */
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SPI_CTRL_CDIV0 = 10, /**< SPI control register(10) (r/w): Clock divider bit 0 */
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SPI_CTRL_CDIV1 = 11, /**< SPI control register(11) (r/w): Clock divider bit 1 */
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SPI_CTRL_CDIV2 = 12, /**< SPI control register(12) (r/w): Clock divider bit 2 */
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SPI_CTRL_CDIV3 = 13, /**< SPI control register(13) (r/w): Clock divider bit 3 */
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SPI_CTRL_FIFO_LSB = 23, /**< SPI control register(23) (r/-): log2(FIFO size), lsb */
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SPI_CTRL_FIFO_MSB = 26, /**< SPI control register(26) (r/-): log2(FIFO size), msb */
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SPI_CTRL_RX_AVAIL = 27, /**< SPI control register(27) (r/-): RX FIFO data available (RX FIFO not empty) */
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SPI_CTRL_TX_EMPTY = 28, /**< SPI control register(28) (r/-): TX FIFO empty */
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SPI_CTRL_TX_HALF = 29, /**< SPI control register(29) (r/-): TX FIFO at least half full */
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SPI_CTRL_TX_FULL = 30, /**< SPI control register(30) (r/-): TX FIFO full */
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SPI_CTRL_BUSY = 31 /**< SPI control register(31) (r/-): SPI busy flag */
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SPI_CTRL_RX_AVAIL = 15, /**< SPI control register(15) (r/-): RX FIFO data available (RX FIFO not empty) */
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SPI_CTRL_TX_EMPTY = 16, /**< SPI control register(16) (r/-): TX FIFO empty */
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SPI_CTRL_TX_NHALF = 17, /**< SPI control register(17) (r/-): TX FIFO not at least half full */
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SPI_CTRL_TX_FULL = 18, /**< SPI control register(18) (r/-): TX FIFO full */
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SPI_CTRL_IRQ_RX_AVAIL = 19, /**< SPI control register(19) (r/w): Fire IRQ if RX FIFO data available (RX FIFO not empty) */
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SPI_CTRL_IRQ_TX_EMPTY = 20, /**< SPI control register(20) (r/w): Fire IRQ if TX FIFO empty */
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SPI_CTRL_IRQ_TX_HALF = 21, /**< SPI control register(21) (r/w): Fire IRQ if TX FIFO not at least half full */
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SPI_CTRL_FIFO_LSB = 23, /**< SPI control register(23) (r/-): log2(FIFO size), lsb */
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SPI_CTRL_FIFO_MSB = 26, /**< SPI control register(26) (r/-): log2(FIFO size), msb */
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SPI_CTRL_BUSY = 31 /**< SPI control register(31) (r/-): SPI busy flag */
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};
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/**@}*/
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@ -3,7 +3,7 @@
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// # ********************************************************************************************* #
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// # BSD 3-Clause License #
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// # #
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// # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
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// # Copyright (c) 2023, Stephan Nolting. All rights reserved. #
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// # #
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// # Redistribution and use in source and binary forms, with or without modification, are #
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// # permitted provided that the following conditions are met: #
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@ -44,16 +44,16 @@
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#define neorv32_spi_h
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// prototypes
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int neorv32_spi_available(void);
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void neorv32_spi_setup(int prsc, int cdiv, int clk_phase, int clk_polarity, int data_size, int irq_config);
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void neorv32_spi_disable(void);
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void neorv32_spi_enable(void);
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int neorv32_spi_get_fifo_depth(void);
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void neorv32_spi_cs_en(int cs);
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void neorv32_spi_cs_dis(void);
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uint32_t neorv32_spi_trans(uint32_t tx_data);
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void neorv32_spi_put_nonblocking(uint32_t tx_data);
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uint32_t neorv32_spi_get_nonblocking(void);
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int neorv32_spi_busy(void);
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int neorv32_spi_available(void);
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void neorv32_spi_setup(int prsc, int cdiv, int clk_phase, int clk_polarity, uint32_t irq_mask);
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void neorv32_spi_disable(void);
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void neorv32_spi_enable(void);
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int neorv32_spi_get_fifo_depth(void);
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void neorv32_spi_cs_en(int cs);
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void neorv32_spi_cs_dis(void);
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uint8_t neorv32_spi_trans(uint8_t tx_data);
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void neorv32_spi_put_nonblocking(uint8_t tx_data);
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uint8_t neorv32_spi_get_nonblocking(void);
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int neorv32_spi_busy(void);
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#endif // neorv32_spi_h
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@ -3,7 +3,7 @@
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// # ********************************************************************************************* #
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// # BSD 3-Clause License #
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// # #
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// # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
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// # Copyright (c) 2023, Stephan Nolting. All rights reserved. #
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// # #
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// # Redistribution and use in source and binary forms, with or without modification, are #
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// # permitted provided that the following conditions are met: #
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@ -67,10 +67,9 @@ int neorv32_spi_available(void) {
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* @prama[in] cdiv Clock divider (0..15).
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* @param[in] clk_phase Clock phase (0=sample on rising edge, 1=sample on falling edge).
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* @param[in] clk_polarity Clock polarity (when idle).
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* @param[in] data_size Data transfer size (0: 8-bit, 1: 16-bit, 2: 24-bit, 3: 32-bit).
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* @param[in] irq_config Interrupt configuration (0,1: PHY transfer done, 2: TX FIFO becomes less than half full, 3: TX FIFO becomes empty).
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* @param[in] irq_mask Interrupt configuration mask (CTRL's irq_* bits).
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**************************************************************************/
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void neorv32_spi_setup(int prsc, int cdiv, int clk_phase, int clk_polarity, int data_size, int irq_config) {
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void neorv32_spi_setup(int prsc, int cdiv, int clk_phase, int clk_polarity, uint32_t irq_mask) {
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NEORV32_SPI->CTRL = 0; // reset
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@ -78,10 +77,9 @@ void neorv32_spi_setup(int prsc, int cdiv, int clk_phase, int clk_polarity, int
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tmp |= (uint32_t)(1 & 0x01) << SPI_CTRL_EN;
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tmp |= (uint32_t)(clk_phase & 0x01) << SPI_CTRL_CPHA;
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tmp |= (uint32_t)(clk_polarity & 0x01) << SPI_CTRL_CPOL;
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tmp |= (uint32_t)(data_size & 0x03) << SPI_CTRL_SIZE0;
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tmp |= (uint32_t)(prsc & 0x07) << SPI_CTRL_PRSC0;
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tmp |= (uint32_t)(cdiv & 0x0f) << SPI_CTRL_CDIV0;
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tmp |= (uint32_t)(irq_config & 0x03) << SPI_CTRL_IRQ0;
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tmp |= (uint32_t)(irq_mask & (0x07 << SPI_CTRL_IRQ_RX_AVAIL));
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NEORV32_SPI->CTRL = tmp;
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}
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@ -157,6 +155,7 @@ void neorv32_spi_cs_en(int cs) {
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* @note The SPI chip select output lines are HIGH when deactivated.
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**************************************************************************/
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void neorv32_spi_cs_dis(void) {
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NEORV32_SPI->CTRL &= ~(1 << SPI_CTRL_CS_EN);
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}
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@ -166,37 +165,37 @@ void neorv32_spi_cs_dis(void) {
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*
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* @note This function is blocking.
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*
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* @param tx_data Transmit data (8/16/24/32-bit, LSB-aligned).
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* @return Receive data (8/16/24/32-bit, LSB-aligned).
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* @param tx_data Transmit data (8-bit, LSB-aligned).
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* @return Receive data (8-bit, LSB-aligned).
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**************************************************************************/
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uint32_t neorv32_spi_trans(uint32_t tx_data) {
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uint8_t neorv32_spi_trans(uint8_t tx_data) {
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NEORV32_SPI->DATA = tx_data; // trigger transfer
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NEORV32_SPI->DATA = (uint32_t)tx_data; // trigger transfer
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while((NEORV32_SPI->CTRL & (1<<SPI_CTRL_BUSY)) != 0); // wait for current transfer to finish
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return NEORV32_SPI->DATA;
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return (uint8_t)NEORV32_SPI->DATA;
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}
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/**********************************************************************//**
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* Initiate SPI TX transfer (non-blocking).
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*
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* @param tx_data Transmit data (8/16/24/32-bit, LSB-aligned).
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* @param tx_data Transmit data (8-bit, LSB-aligned).
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**************************************************************************/
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void neorv32_spi_put_nonblocking(uint32_t tx_data) {
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void neorv32_spi_put_nonblocking(uint8_t tx_data) {
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NEORV32_SPI->DATA = tx_data; // trigger transfer
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NEORV32_SPI->DATA = (uint32_t)tx_data; // trigger transfer
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}
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/**********************************************************************//**
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* Get SPI RX data (non-blocking).
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*
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* @return Receive data (8/16/24/32-bit, LSB-aligned).
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* @return Receive data (8-bit, LSB-aligned).
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**************************************************************************/
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uint32_t neorv32_spi_get_nonblocking(void) {
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uint8_t neorv32_spi_get_nonblocking(void) {
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return NEORV32_SPI->DATA;
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return (uint8_t)NEORV32_SPI->DATA;
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}
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@ -825,35 +825,64 @@
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<bitRange>[2:2]</bitRange>
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<description>Clock polarity</description>
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</field>
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<field>
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<name>SPI_CTRL_SIZE</name>
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<bitRange>[4:3]</bitRange>
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<description>Data transfer size</description>
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</field>
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<field>
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<name>SPI_CTRL_CS_SEL</name>
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<bitRange>[7:5]</bitRange>
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<bitRange>[5:3]</bitRange>
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<description>CS select</description>
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</field>
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<field>
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<name>SPI_CTRL_CS_EN</name>
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<bitRange>[8:8]</bitRange>
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<bitRange>[6:6]</bitRange>
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<description>Enable selected CS line</description>
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</field>
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<field>
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<name>SPI_CTRL_PRSC</name>
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<bitRange>[11:9]</bitRange>
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<bitRange>[9:7]</bitRange>
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<description>Clock prescaler select</description>
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</field>
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<field>
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<name>SPI_CTRL_CDIV</name>
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<bitRange>[15:12]</bitRange>
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<bitRange>[13:10]</bitRange>
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<description>SPI clock divider</description>
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</field>
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<field>
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<name>SPI_CTRL_IRQ</name>
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<bitRange>[17:16]</bitRange>
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<description>Interrupt configuration</description>
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<name>SPI_CTRL_RX_AVAIL</name>
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<bitRange>[15:15]</bitRange>
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<access>read-only</access>
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<description>RX FIFO data available (RX FIFO not empty)</description>
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</field>
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<field>
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<name>SPI_CTRL_TX_EMPTY</name>
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<bitRange>[16:16]</bitRange>
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<access>read-only</access>
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<description>TX FIFO is empty</description>
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</field>
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<field>
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<name>SPI_CTRL_TX_NHALF</name>
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<bitRange>[17:17]</bitRange>
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<access>read-only</access>
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<description>TX FIFO not at least half full</description>
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</field>
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<field>
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<name>SPI_CTRL_TX_FULL</name>
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<bitRange>[18:18]</bitRange>
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<access>read-only</access>
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<description>TX FIFO is full</description>
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</field>
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<field>
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<name>SPI_CTRL_IRQ_RX_AVAIL</name>
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<bitRange>[19:19]</bitRange>
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<description>Fire interrupt if RX FIFO is not empty</description>
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</field>
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<field>
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<name>SPI_CTRL_IRQ_TX_EMPTY</name>
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<bitRange>[20:20]</bitRange>
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<description>Fire interrupt if TX FIFO is empty</description>
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</field>
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<field>
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<name>SPI_CTRL_IRQ_TX_NHALF</name>
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<bitRange>[21:21]</bitRange>
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<description>Fire interrupt if TX FIFO is not at least half full</description>
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</field>
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<field>
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<name>SPI_CTRL_FIFO</name>
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@ -861,30 +890,6 @@
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<access>read-only</access>
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<description>log2(FIFO size)</description>
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</field>
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<field>
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<name>SPI_CTRL_RX_AVAIL</name>
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<bitRange>[27:27]</bitRange>
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<access>read-only</access>
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<description>RX FIFO data available (RX FIFO not empty)</description>
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</field>
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<field>
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<name>SPI_CTRL_TX_EMPTY</name>
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<bitRange>[28:28]</bitRange>
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<access>read-only</access>
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<description>TX FIFO is empty</description>
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</field>
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<field>
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<name>SPI_CTRL_TX_HALF</name>
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<bitRange>[29:29]</bitRange>
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<access>read-only</access>
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<description>TX FIFO is at least half full</description>
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</field>
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<field>
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<name>SPI_CTRL_TX_FULL</name>
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<bitRange>[30:30]</bitRange>
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<access>read-only</access>
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<description>TX FIFO is full</description>
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</field>
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<field>
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<name>SPI_CTRL_BUSY</name>
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<bitRange>[31:31]</bitRange>
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