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[top] remove clock gating generic

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stnolting 2025-03-21 19:47:22 +01:00
parent d3b7e65777
commit 40bccf4671
5 changed files with 1 additions and 8 deletions
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1
docs/datasheet/soc.adoc
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@ -237,7 +237,6 @@ The generic type "`suv(x:y)`" is an abbreviation for "`std_ulogic_vector(x downt
| `RISCV_ISA_Zmmul` | boolean | false | Enable <<_zmmul_isa_extension>> (hardware-based integer multiplication).
| `RISCV_ISA_Zxcfu` | boolean | false | Enable NEORV32-specific <<_zxcfu_isa_extension>> (custom RISC-V instructions).
4+^| **<<_cpu_tuning_options>>**
| `CPU_CLOCK_GATING_EN` | boolean | false | Implement sleep-mode clock gating; see sections <<_sleep_mode>> and <<_cpu_clock_gating>>.
| `CPU_FAST_MUL_EN` | boolean | false | Implement fast but large full-parallel multipliers (trying to infer DSP blocks); see section <<_cpu_arithmetic_logic_unit>>.
| `CPU_FAST_SHIFT_EN` | boolean | false | Implement fast but large full-parallel barrel shifters; see section <<_cpu_arithmetic_logic_unit>>.
| `CPU_RF_HW_RST_EN` | boolean | false | Implement full hardware reset for register file (use individual FFs instead of BRAM); see section <<_cpu_register_file>>.

3
rtl/core/neorv32_package.vhd
View file

@ -29,7 +29,7 @@ package neorv32_package is
-- Architecture Constants -----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01110200"; -- hardware version
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01110201"; -- hardware version
constant archid_c : natural := 19; -- official RISC-V architecture ID
constant XLEN : natural := 32; -- native data path width
@ -823,7 +823,6 @@ package neorv32_package is
RISCV_ISA_Zksh : boolean := false;
RISCV_ISA_Zxcfu : boolean := false;
-- Tuning Options --
CPU_CLOCK_GATING_EN : boolean := false;
CPU_FAST_MUL_EN : boolean := false;
CPU_FAST_SHIFT_EN : boolean := false;
CPU_RF_HW_RST_EN : boolean := false;

2
rtl/core/neorv32_top.vhd
View file

@ -62,7 +62,6 @@ entity neorv32_top is
RISCV_ISA_Zxcfu : boolean := false; -- implement custom (instr.) functions unit
-- Tuning Options --
CPU_CLOCK_GATING_EN : boolean := false; -- enable clock gating when in sleep mode
CPU_FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
CPU_FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
CPU_RF_HW_RST_EN : boolean := false; -- implement full hardware reset for register file
@ -522,7 +521,6 @@ begin
RISCV_ISA_Sdtrig => OCD_EN,
RISCV_ISA_Smpmp => cpu_smpmp_c,
-- Tuning Options --
CPU_CLOCK_GATING_EN => CPU_CLOCK_GATING_EN,
CPU_FAST_MUL_EN => CPU_FAST_MUL_EN,
CPU_FAST_SHIFT_EN => CPU_FAST_SHIFT_EN,
CPU_RF_HW_RST_EN => CPU_RF_HW_RST_EN,

1
rtl/system_integration/neorv32_vivado_ip.vhd
View file

@ -371,7 +371,6 @@ begin
RISCV_ISA_Zksh => RISCV_ISA_Zksh,
RISCV_ISA_Zxcfu => RISCV_ISA_Zxcfu,
-- Extension Options --
CPU_CLOCK_GATING_EN => false, -- clock gating is not supported here
CPU_FAST_MUL_EN => CPU_FAST_MUL_EN,
CPU_FAST_SHIFT_EN => CPU_FAST_SHIFT_EN,
CPU_RF_HW_RST_EN => CPU_RF_HW_RST_EN,

2
sim/neorv32_tb.vhd
View file

@ -46,7 +46,6 @@ entity neorv32_tb is
RISCV_ISA_Zksh : boolean := true; -- implement ShangMi hash extension
RISCV_ISA_Zmmul : boolean := true; -- implement multiply-only M sub-extension
RISCV_ISA_Zxcfu : boolean := true; -- implement custom (instr.) functions unit
CPU_CLOCK_GATING_EN : boolean := true; -- enable clock gating when in sleep mode
CPU_FAST_MUL_EN : boolean := true; -- use DSPs for M extension's multiplier
CPU_FAST_SHIFT_EN : boolean := true; -- use barrel shifter for shift operations
CPU_RF_HW_RST_EN : boolean := false; -- implement full hardware reset for register file
@ -156,7 +155,6 @@ begin
RISCV_ISA_Zmmul => RISCV_ISA_Zmmul,
RISCV_ISA_Zxcfu => RISCV_ISA_Zxcfu,
-- Extension Options --
CPU_CLOCK_GATING_EN => CPU_CLOCK_GATING_EN,
CPU_FAST_MUL_EN => CPU_FAST_MUL_EN,
CPU_FAST_SHIFT_EN => CPU_FAST_SHIFT_EN,
CPU_RF_HW_RST_EN => CPU_RF_HW_RST_EN,