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[mxisa csr] add Zb* ISA estensions
relocate tuning options flags
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stnolting
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4 changed files with 36 additions and 20 deletions
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@ -934,7 +934,7 @@ outside of machine-mode will raise an illegal instruction exception.
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[cols="<1,<8"]
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[frame="topbot",grid="none"]
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|=======================
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| Name | Machine extended isa and extensions register
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| Name | Machine extended ISA and extensions register
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| Address | `0xfc0`
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| Reset value | `DEFINED`
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| ISA | `Zicsr` & `X`
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@ -969,10 +969,12 @@ discover ISA sub-extensions and CPU configuration options
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| 19 | `CSR_MXISA_ZKSH` | r/- | <<_zksh_isa_extension>> available
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| 20 | `CSR_MXISA_ZKSED` | r/- | <<_zksed_isa_extension>> available
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| 21 | `CSR_MXISA_ZKS` | r/- | <<_zks_isa_extension>> available
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| 23:22 | - | r/- | hardwired to zero
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| 24 | `CSR_MXISA_IS_SIM` | r/- | set if CPU is being **simulated** (⚠️ not guaranteed)
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| 28:25 | - | r/- | hardwired to zero
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| 29 | `CSR_MXISA_RFHWRST` | r/- | full hardware reset of register file available when set (`REGFILE_HW_RST`)
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| 30 | `CSR_MXISA_FASTMUL` | r/- | fast multiplication available when set (`FAST_MUL_EN`)
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| 31 | `CSR_MXISA_FASTSHIFT` | r/- | fast shifts available when set (`FAST_SHIFT_EN`)
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| 22 | `CSR_MXISA_ZBA` | r/- | <<_zba_isa_extension>> available
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| 23 | `CSR_MXISA_ZBB` | r/- | <<_zbb_isa_extension>> available
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| 24 | `CSR_MXISA_ZBS` | r/- | <<_zbs_isa_extension>> available
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| 27:25 | - | r/- | _reserved_, hardwired to zero
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| 28 | `CSR_MXISA_RFHWRST` | r/- | full hardware reset of register file available when set (`REGFILE_HW_RST`)
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| 29 | `CSR_MXISA_FASTMUL` | r/- | fast multiplication available when set (`FAST_MUL_EN`)
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| 30 | `CSR_MXISA_FASTSHIFT` | r/- | fast shifts available when set (`FAST_SHIFT_EN`)
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| 31 | `CSR_MXISA_IS_SIM` | r/- | set if CPU is being **simulated** (⚠️ not guaranteed)
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|=======================
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@ -41,9 +41,12 @@ entity neorv32_cpu_control is
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RISCV_ISA_E : boolean; -- implement embedded-class register file extension
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RISCV_ISA_M : boolean; -- implement mul/div extension
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RISCV_ISA_U : boolean; -- implement user mode extension
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RISCV_ISA_Zba : boolean; -- implement shifted-add bit-manipulation extension
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RISCV_ISA_Zbb : boolean; -- implement basic bit-manipulation extension
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RISCV_ISA_Zbkb : boolean; -- implement bit-manipulation instructions for cryptography
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RISCV_ISA_Zbkc : boolean; -- implement carry-less multiplication instructions
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RISCV_ISA_Zbkx : boolean; -- implement cryptography crossbar permutation extension?
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RISCV_ISA_Zbs : boolean; -- implement single-bit bit-manipulation extension
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RISCV_ISA_Zfinx : boolean; -- implement 32-bit floating-point extension
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RISCV_ISA_Zicntr : boolean; -- implement base counters
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RISCV_ISA_Zicond : boolean; -- implement integer conditional operations
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@ -1893,7 +1896,7 @@ begin
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csr.rdata(7) <= bool_to_ulogic_f(RISCV_ISA_Zicntr); -- Zicntr: base counters
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csr.rdata(8) <= bool_to_ulogic_f(RISCV_ISA_Smpmp); -- Smpmp: physical memory protection
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csr.rdata(9) <= bool_to_ulogic_f(RISCV_ISA_Zihpm); -- Zihpm: hardware performance monitors
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csr.rdata(10) <= bool_to_ulogic_f(RISCV_ISA_Sdext); -- Sdext: RISC-V (external) debug mode
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csr.rdata(10) <= bool_to_ulogic_f(RISCV_ISA_Sdext); -- Sdext: RISC-V external debug
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csr.rdata(11) <= bool_to_ulogic_f(RISCV_ISA_Sdtrig); -- Sdtrig: trigger module
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csr.rdata(12) <= bool_to_ulogic_f(RISCV_ISA_Zbkx); -- Zbkx: cryptography crossbar permutation
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csr.rdata(13) <= bool_to_ulogic_f(RISCV_ISA_Zknd); -- Zknd: cryptography NIST AES decryption
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@ -1905,12 +1908,19 @@ begin
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csr.rdata(19) <= bool_to_ulogic_f(RISCV_ISA_Zksh); -- Zksh: ShangMi hash functions
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csr.rdata(20) <= bool_to_ulogic_f(RISCV_ISA_Zksed); -- Zksed: ShangMi block cyphers
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csr.rdata(21) <= bool_to_ulogic_f(RISCV_ISA_Zks); -- Zks: ShangMi algorithm suite
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-- misc --
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csr.rdata(24) <= bool_to_ulogic_f(is_simulation_c); -- is this a simulation?
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csr.rdata(22) <= bool_to_ulogic_f(RISCV_ISA_Zba); -- Zba: shifted-add bit-manipulation
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csr.rdata(23) <= bool_to_ulogic_f(RISCV_ISA_Zbb); -- Zbb: basic bit-manipulation extension
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csr.rdata(24) <= bool_to_ulogic_f(RISCV_ISA_Zbs); -- Zbs: single-bit bit-manipulation extension
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-- reserved --
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csr.rdata(25) <= '0';
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csr.rdata(26) <= '0';
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csr.rdata(27) <= '0';
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-- tuning options --
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csr.rdata(29) <= bool_to_ulogic_f(REGFILE_HW_RST); -- full hardware reset of register file
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csr.rdata(30) <= bool_to_ulogic_f(FAST_MUL_EN); -- DSP-based multiplication (M extensions only)
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csr.rdata(31) <= bool_to_ulogic_f(FAST_SHIFT_EN); -- parallel logic for shifts (barrel shifters)
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csr.rdata(28) <= bool_to_ulogic_f(REGFILE_HW_RST); -- full hardware reset of register file
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csr.rdata(29) <= bool_to_ulogic_f(FAST_MUL_EN); -- DSP-based multiplication (M extensions only)
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csr.rdata(30) <= bool_to_ulogic_f(FAST_SHIFT_EN); -- parallel logic for shifts (barrel shifters)
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-- misc --
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csr.rdata(31) <= bool_to_ulogic_f(is_simulation_c); -- is this a simulation?
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-- --------------------------------------------------------------------
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-- undefined/unavailable
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@ -329,14 +329,15 @@ enum NEORV32_CSR_XISA_enum {
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CSR_MXISA_ZKSH = 19, /**< CPU mxisa CSR (19): scalar cryptography - ShangMi hash functions (r/-)*/
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CSR_MXISA_ZKSED = 20, /**< CPU mxisa CSR (20): scalar cryptography - ShangMi block cyphers (r/-)*/
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CSR_MXISA_ZKS = 21, /**< CPU mxisa CSR (21): scalar cryptography - ShangMi algorithm suite (r/-)*/
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// Misc
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CSR_MXISA_IS_SIM = 24, /**< CPU mxisa CSR (24): this might be a simulation when set (r/-)*/
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CSR_MXISA_ZBA = 22, /**< CPU mxisa CSR (22): shifted-add bit-manipulation operation (r/-)*/
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CSR_MXISA_ZBB = 23, /**< CPU mxisa CSR (23): basic bit-manipulation operation (r/-)*/
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CSR_MXISA_ZBS = 24, /**< CPU mxisa CSR (24): single-bit bit-manipulation operation (r/-)*/
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// Tuning options
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CSR_MXISA_RFHWRST = 29, /**< CPU mxisa CSR (29): Register file has full hardware reset (r/-)*/
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CSR_MXISA_FASTMUL = 30, /**< CPU mxisa CSR (30): DSP-based multiplication (M extensions only) (r/-)*/
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CSR_MXISA_FASTSHIFT = 31 /**< CPU mxisa CSR (31): parallel logic for shifts (barrel shifters) (r/-)*/
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CSR_MXISA_RFHWRST = 28, /**< CPU mxisa CSR (28): register file has full hardware reset (r/-)*/
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CSR_MXISA_FASTMUL = 29, /**< CPU mxisa CSR (29): DSP-based multiplication (M extensions only) (r/-)*/
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CSR_MXISA_FASTSHIFT = 30, /**< CPU mxisa CSR (30): parallel logic for shifts (barrel shifters) (r/-)*/
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// Misc
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CSR_MXISA_IS_SIM = 31 /**< CPU mxisa CSR (31): this might be a simulation when set (r/-)*/
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};
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@ -450,9 +450,12 @@ void neorv32_rte_print_hw_config(void) {
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if (tmp & (1<<CSR_MXISA_SDEXT)) { neorv32_uart0_printf("Sdext "); }
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if (tmp & (1<<CSR_MXISA_SDTRIG)) { neorv32_uart0_printf("Sdtrig "); }
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if (tmp & (1<<CSR_MXISA_SMPMP)) { neorv32_uart0_printf("Smpmp "); }
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if (tmp & (1<<CSR_MXISA_ZBA)) { neorv32_uart0_printf("Zba "); }
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if (tmp & (1<<CSR_MXISA_ZBB)) { neorv32_uart0_printf("Zbb "); }
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if (tmp & (1<<CSR_MXISA_ZBKB)) { neorv32_uart0_printf("Zbkb "); }
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if (tmp & (1<<CSR_MXISA_ZBKC)) { neorv32_uart0_printf("Zbkc "); }
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if (tmp & (1<<CSR_MXISA_ZBKX)) { neorv32_uart0_printf("Zbkx "); }
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if (tmp & (1<<CSR_MXISA_ZBS)) { neorv32_uart0_printf("Zbs "); }
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if (tmp & (1<<CSR_MXISA_ZFINX)) { neorv32_uart0_printf("Zfinx "); }
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if (tmp & (1<<CSR_MXISA_ZICNTR)) { neorv32_uart0_printf("Zicntr "); }
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if (tmp & (1<<CSR_MXISA_ZICOND)) { neorv32_uart0_printf("Zicond "); }
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