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[docs/datasheet, README] added project rationale (first draft)
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@ -36,6 +36,8 @@ The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC
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The project is intended as auxiliary processor in larger SoC designs or as *ready-to-go* stand-alone
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custom / customizable microcontroller.
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:information_source: Want to know more? Check out the [project's rationale](https://stnolting.github.io/neorv32/#_rationale).
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:books: For detailed information take a look at the [NEORV32 documentation (online at GitHub-pages)](https://stnolting.github.io/neorv32/).
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The *doxygen*-based documentation of the *software framework* is also available online
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at [GitHub-pages](https://stnolting.github.io/neorv32/sw/files.html).
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@ -288,6 +290,8 @@ This overview provides some *quick links* to the most important sections of the
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### :electric_plug: Hardware Overview
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* [Rationale](https://stnolting.github.io/neorv32/#_rationale) - NEORV32: why, how come, what for
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* [NEORV32 Processor](https://stnolting.github.io/neorv32/#_neorv32_processor_soc) - the SoC
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* [Top Entity - Signals](https://stnolting.github.io/neorv32/#_processor_top_entity_signals) - how to connect to the processor
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* [Top Entity - Generics](https://stnolting.github.io/neorv32/#_processor_top_entity_generics) - configuration options
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@ -1,11 +1,6 @@
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:sectnums:
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== Overview
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[quote]
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____
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RISC-V - Instruction Sets Want To Be Free!
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____
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The NEORV32footnote:[Pronounced "neo-R-V-thirty-two" or "neo-risc-five-thirty-two" in its long form.] is an open-source
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RISC-V compatible processor system that is intended as *ready-to-go* auxiliary processor within a larger SoC
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designs or as stand-alone custom / customizable microcontroller.
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@ -24,8 +19,6 @@ default toolchain (https://github.com/stnolting/riscv-gcc-prebuilt[prebuilt tool
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The project's change log is available in https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md[CHANGELOG.md]
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in the root directory of the NEORV32 repository. Please also check out the <<_legal>> section.
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:sectnums!:
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=== Structure
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@ -58,24 +51,93 @@ Links in this document are <<_structure,highlighted>>.
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<<<
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// ####################################################################################################################
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:sectnums:
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=== Rationale
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**Why did you make this?**
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I am fascinated by processor and CPU architecture design: it is the magic frontier where software meets hardware.
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This project has started as something like a _journey_ into this magic realm to understand how things actually work
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down on this very low level.
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But there is more! When I started to dive into the emerging RISC-V ecosystem I felt overwhelmed by the complexity.
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As a beginner it is hard to get an overview - especially when you want to setup a minimal platform to tinker with:
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Which core to use? How to get the right toolchain? What features do I need? How does the booting work? How do I
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create an actual executable? How to get that into the hardware? How to customize things? **_Where to start???_**
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So this project aims to provides a _simple to understand_ and _easy to use_ yet _powerful_ and _flexible_ platform
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that targets FPGA and RISC-V beginners as well as advanced users. Join me and us on this journey! 🙃
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**Why a _soft_-core processor?**
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As a matter of fact soft-core processors _cannot_ compete with discrete or FPGA hard-macro processors in terms
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of performance, energy and size. But they do fill a niche in FPGA design space. For example, soft-core processors
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allow to implement the _control flow part_ of certain applications (like communication protocol handling) using
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software like plain C. This provides high flexibility as software can be easily changed, re-compiled and
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re-uploaded again.
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Furthermore, the concept of flexibility applies to all aspects of a soft-core processor. The user can add
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_exactly_ the features that are required by the application: additional memories, custom interfaces, specialized
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IP and even user-defined instructions.
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**Why RISC-V?**
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[quote, RISC-V International, https://riscv.org/about/]
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____
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RISC-V is a free and open ISA enabling a new era of processor innovation through open standard collaboration.
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____
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I love the idea of open-source. **Knowledge can help best if it is freely available.**
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While open-source has already become quite popular in _software_, hardware projects still need to catch up.
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Admittedly, there has been quite a development, but mainly in terms of _platforms_ and _applications_ (so
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schematics, PCBs, etc.). Although processors and CPUs are the heart of almost every digital system, having a true
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open-source silicon is still a rarity. RISC-V aims to change that. Even it is _just one approach_, it helps paving
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the road for future development.
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Furthermore, I welcome the community aspect of RISC-V. The ISA and everything beyond is developed with direct
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contact to the community: this includes businesses and professionals but also hobbyist, amateurs and people
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that are just curious. Everyone can join discussions and contribute to RISC-V in their very own way.
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Finally, I really like the RISC-V ISA itself. It aims to be a clean, orthogonal and "intuitive" ISA that
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resembles with the basic concepts of _RISC_: simple yet effective.
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**Yet another RISC-V core? What makes it special?**
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The NEORV32 is not based on another RISC-V core. It was build entirely from ground up (just following the official
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ISA specs) having a different design goal in mind. The project does not intend to replace certain RISC-V cores or
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just beat existing ones like https://github.com/SpinalHDL/VexRiscv[VexRISC] in terms of performance or
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https://github.com/olofk/serv[SERV] in terms of size.
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The project aims to provide _another option_ in the RISC-V / soft-core design space with a different performance
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vs. size trade-off and a different focus: _embrace_ concepts like documentation, platform-independence / portability,
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RISC-V compatibility, _customization_ and _ease of use_. See the <<_project_key_features>> below.
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// ####################################################################################################################
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:sectnums:
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=== Project Key Features
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* **NEORV32 CPU**: 32-bit `rv32i` RISC-V CPU - passes the official RISC-V architecture tests
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* official https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md[RISC-V open source architecture ID]
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* optional RISC-V CPU extensions:
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** `A` - atomic memory access operations
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** `B` - bit-manipulation instructions
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** `C` - 16-bit compressed instructions
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** `E` - embedded CPU version (reduced register file size)
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** `M` - integer multiplication and division hardware
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** `U` - less-privileged _user_ mode
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** `Zfinx` - single-precision floating-point unit
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** `Zicsr` - control and status register access (privileged architecture)
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** `Zifencei` - instruction stream synchronization
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** `PMP` - physical memory protection
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** `HPM` - hardware performance monitors
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* open-source and documented; including user guides to get started
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* completely described in behavioral, platform-independent VHDL (yet platform-optimized modules are provided)
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* fully synchronous design, no latches, no gated clocks
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* small hardware footprint and high operating frequency for easy integration
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* **NEORV32 CPU**: 32-bit `rv32i` RISC-V CPU
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** RISC-V compatibility: passes the official architecture tests
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** base architecture + privileged architecture (optional) + ISA extensions (optional)
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** rich set of customization options (ISA extensions, design goal: performance / area (/ energy), ...)
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** official https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md[RISC-V open source architecture ID]
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* **NEORV32 Processor (SoC)**: highly-configurable full-scale microcontroller-like processor system
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** based on the NEORV32 CPU
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** optional serial interfaces (UARTs, TWI, SPI)
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** optional timers and counters (WDT, MTIME, NCO)
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** optional general purpose IO and PWM and native NeoPixel (c) compatible smart LED interface
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** optional embedded memories / caches for data, instructions and bootloader
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** optional external memory interface for custom connectivity (Wishbone or AXI4-Lite)
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** on-chip debugger compatible with OpenOCD and gdb
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* **Software framework**
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** GCC-based toolchain - prebuilt toolchains available; application compilation based on GNU makefiles
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** internal bootloader with serial user interface
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@ -83,16 +145,10 @@ Links in this document are <<_structure,highlighted>>.
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** runtime environment and several example programs
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** doxygen-based documentation of the software framework; a deployed version is available at https://stnolting.github.io/neorv32/sw/files.html
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** FreeRTOS port + demos available
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* **NEORV32 Processor**: highly-configurable full-scale microcontroller-like processor system / SoC based on the NEORV32 CPU with optional standard peripherals:
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** serial interfaces (UARTs, TWI, SPI)
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** timers and counters (WDT, MTIME, NCO)
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** general purpose IO and PWM and native NeoPixel (c) compatible smart LED interface
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** embedded memories / caches for data, instructions and bootloader
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** external memory interface (Wishbone or AXI4-Lite)
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* on-chip debugger compatible with OpenOCD and gdb
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* fully synchronous design, no latches, no gated clocks
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* completely described in behavioral, platform-independent VHDL
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* small hardware footprint and high operating frequency
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[TIP]
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For more in-depth details regarding the feature provided by he hardware see the according sections:
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<<_neorv32_central_processing_unit_cpu>> and <<_neorv32_processor_soc>>.
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<<<
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@ -104,6 +160,7 @@ Links in this document are <<_structure,highlighted>>.
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neorv32 - Project home folder
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├.ci - Scripts for continuous integration
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├setups - Example setups for various FPGA boards and toolchains
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│└...
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├CHANGELOG.md - Project change log
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├docs - Project documentation
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│├doxygen_build - Software framework documentation (generated by doxygen)
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